component
LM5117QPSQX
Public Made by Adomby adom
Texas Instruments DC-DC Converters, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5117QPSQX
Texas Instruments · DC-DC Converters · WQFN-24-EP(4x4)
LM5117QPSQX from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DEMB | input | Optional logic input that enables diode emulation when low and disables it when high; an internal 50-kΩ pull-down holds it low (diode emulation enabled) if left floating. |
| 2 | RES | output | Restart timer pin for hiccup-mode current limiting; a capacitor sets the off time, charged by a 10-μA source to the 1.25 V threshold after 256 consecutive cycle-by-cycle current-limit cycles. |
| 3 | SS | input | Soft-start pin where an external capacitor and an internal 10-μA current source set the error amplifier reference ramp rate; held low when VCC < 5 V, UVLO < 1.25 V or during thermal shutdown. |
| 4 | RT | input | Oscillator programming pin with a single resistor to AGND (recommended maximum 750 kHz), which can be synchronized to an external clock by coupling a positive pulse through a small capacitor. |
| 5 | AGND | power_in | Analog ground, return for the internal 0.8 V voltage reference and analog circuits. |
| 6 | NC | unconnected | No electrical contact. |
| 7 | VCCDIS | input | Optional input that disables the internal VCC regulator when above 1.25 V; has an internal 500-kΩ pull-down that enables the regulator when left floating. |
| 8 | FB | input | Inverting input of the internal error amplifier; a resistor divider from the output sets the voltage, with a 0.8 V regulation threshold. |
| 9 | COMP | output | Output of the internal error amplifier; the loop compensation network is connected between this pin and FB. |
| 10 | CM | output | Current monitor output providing the average sensed inductor current, monitored between CM and AGND; leave floating when unused. |
| 11 | RAMP | input | PWM ramp signal input; an external resistor and capacitor from SW to RAMP and AGND set the ramp slope, emulating the inductor AC current with slope proportional to input voltage. |
| 12 | CS | input | Current sense amplifier input, connected to the high side of the current sense resistor. |
| 13 | CSG | power_in | Kelvin ground connection to the current sense resistor, connected directly to its low side. |
| 14 | PGND | power_in | Power ground return for the low-side NMOS gate driver, connected directly to the low side of the current sense resistor. |
| 15 | LO | output | Low-side NMOS gate drive output, connected to the gate of the low-side synchronous NMOS through a short, low inductance path. |
| 16 | VCC | power_in | Bias supply pin, to be locally decoupled to PGND with a low ESR/ESL capacitor placed as close to the controller as possible. |
| 17 | NC | unconnected | No electrical contact. |
| 18 | SW | output | Switching node of the buck regulator, connected to the bootstrap capacitor, the high-side NMOS source and the low-side NMOS drain through a short, low inductance path. |
| 19 | HO | output | High-side NMOS gate drive output, connected to the gate of the high-side NMOS through a short, low inductance path. |
| 20 | HB | power_in | High-side driver supply for the bootstrap gate drive, connected to the bootstrap diode cathode and bootstrap capacitor placed close to the controller. |
| 21 | NC | unconnected | No electrical contact. |
| 22 | VIN | power_in | Supply voltage input source for the VCC regulator (recommended 5.5 V to 65 V). |
| 23 | NC | unconnected | No electrical contact. |
| 24 | UVLO | input | Undervoltage lockout programming pin: shutdown below 0.4 V, standby between 0.4 V and 1.25 V, and switching enabled above 1.25 V, where a 20-μA hysteresis current source turns on. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
LM5117QPSQX - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm - 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
lm5117qpsqx-etched.step/lm5117qpsqx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5117qpsqx.step/lm5117qpsqx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
9e27f24e84faebf5, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).