component
LM5117QPMHX
Public Made by Adomby adom
Texas Instruments DC-DC Controllers, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5117QPMHX
Texas Instruments · DC-DC Controllers · HTSSOP-20-EP
LM5117QPMHX from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | UVLO | input | Undervoltage lockout programming pin: below 0.4 V the regulator shuts down, 0.4 V to 1.25 V gives standby with no switching, and above 1.25 V switching is enabled with a 20μA source flowing through the external UVLO resistors for hysteresis. |
| 2 | DEMB | input | Optional logic input that enables diode emulation when low and disables it when high, with an internal 50-kΩ pull-down that enables diode emulation if the pin is left floating. |
| 3 | RES | output | Restart timer pin whose capacitor sets the off time of hiccup-mode current limiting; hiccup starts after 256 consecutive PWM cycles of cycle-by-cycle current limiting and a 10μA source charges the capacitor to 1.25 V to restart the controller. |
| 4 | SS | input | Soft-start pin where an external capacitor and an internal 10μA source set the ramp rate of the error amplifier reference, and the pin is held low when VCC is below 5 V, UVLO is below 1.25 V, or during thermal shutdown. |
| 5 | RT | input | Oscillator timing pin programmed by a single resistor to AGND, with a recommended maximum oscillator frequency of 750 kHz, and the oscillator can be synchronized by coupling a positive pulse through a small capacitor. |
| 6 | AGND | power_in | Analog ground, the return for the internal 0.8 V voltage reference and analog circuits. |
| 7 | VCCDIS | input | Optional input that disables the internal VCC regulator when above 1.25 V, with an internal 500-kΩ pull-down that keeps the regulator enabled when the pin is left floating. |
| 8 | FB | input | Inverting input of the internal error amplifier, where a resistor divider from the output sets the output voltage against a regulation threshold of 0.8 V. |
| 9 | COMP | output | Output of the internal error amplifier, with the loop compensation network connected between this pin and FB. |
| 10 | CM | output | Current monitor output that provides the average of the sensed inductor current, to be connected directly between CM and AGND and left floating when unused. |
| 11 | RAMP | input | PWM ramp signal pin where an external resistor and capacitor between SW, RAMP and AGND set a ramp slope proportional to input supply voltage. |
| 12 | CS | input | Current sense amplifier input, connected to the high side of the current sense resistor. |
| 13 | CSG | power_in | Kelvin ground connection to the current sense resistor, connected directly to its low side. |
| 14 | PGND | power_in | Power ground return for the low-side NMOS gate driver, connected directly to the low side of the current sense resistor. |
| 15 | LO | output | Low-side NMOS gate drive output, connected to the low-side synchronous NMOS gate through a short, low-inductance path. |
| 16 | VCC | power_in | Bias supply pin with a 5.5 V to 14 V recommended range, to be locally decoupled to PGND with a low ESR/ESL capacitor placed as close to the controller as possible. |
| 17 | SW | output | Switching node of the buck regulator, connected to the bootstrap capacitor, high-side NMOS source and low-side NMOS drain through a short, low-inductance path, with an absolute maximum range of -3.0 V to 75 V to AGND. |
| 18 | HO | output | High-side NMOS gate drive output, connected to the high-side NMOS gate through a short, low-inductance path. |
| 19 | HB | power_in | High-side driver supply for the bootstrap gate drive, connected to the bootstrap diode cathode and bootstrap capacitor, which should be placed as close to the controller as possible, with a recommended HB to SW range of 5.5 V to 14 V. |
| 20 | VIN | power_in | Supply voltage input for the VCC regulator, with a recommended operating range of 5.5 V to 65 V. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Supply Chip |
| Pins | 21 |
CAD (KiCad official)
- Symbol:
LM5117QPMHX - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lm5117qpmhx-etched.step/lm5117qpmhx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5117qpmhx.step/lm5117qpmhx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (49 pp, sha256
9e27f24e84faebf5, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).