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LM5117PSQX

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Texas Instruments DC-DC Controllers, WQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM5117PSQX

Texas Instruments · DC-DC Controllers · WQFN-24-EP(4x4)

LM5117PSQX from Texas Instruments, in a WQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DEMB input Optional logic input that enables diode emulation when low and disables it when high; an internal 50-kΩ pull-down holds it low (diode emulation enabled) if left floating.
2 RES output Restart timer pin whose capacitor sets the off time before restart in hiccup mode, which begins after 256 consecutive PWM cycles of cycle-by-cycle current limiting, with a 10-μA source charging it to the 1.25 V threshold.
3 SS input Soft-start pin where an external capacitor and an internal 10-μA current source set the ramp rate of the error amplifier reference, and which is held low when VCC is below 5 V, UVLO is below 1.25 V, or during thermal shutdown.
4 RT input Oscillator timing pin programmed by a single resistor to AGND, with a recommended maximum oscillator frequency of 750 kHz, and which can be synchronized to an external clock through a small coupling capacitor.
5 AGND power_in Analog ground that serves as the return for the internal 0.8 V voltage reference and analog circuits.
6 NC unconnected No electrical contact.
7 VCCDIS input Optional input that disables the internal VCC regulator when above 1.25 V, has an internal 500-kΩ pull-down that enables the regulator when floating, and can be overridden by pulling it above 1.25 V from an external bias.
8 FB input Feedback input to the inverting input of the internal error amplifier, where a resistor divider from the output sets the output voltage against the 0.8 V regulation threshold.
9 COMP output Output of the internal error amplifier, with the loop compensation network connected between this pin and FB.
10 CM output Current monitor output that provides the average of the sensed inductor current, monitored directly between CM and AGND, and left floating when unused.
11 RAMP input PWM ramp input where an external resistor and capacitor between SW, RAMP and AGND set the ramp slope that emulates the inductor AC current in proportion to input voltage.
12 CS input Current sense amplifier input that connects to the high side of the current sense resistor.
13 CSG power_in Kelvin ground connection that connects directly to the low side of the current sense resistor.
14 PGND power_in Power ground return for the low-side NMOS gate driver that connects directly to the low side of the current sense resistor.
15 LO output Low-side NMOS gate drive output that connects to the low-side synchronous NMOS gate through a short, low-inductance path.
16 VCC power_in Bias supply pin that must be decoupled to PGND with a low-ESR/ESL capacitor placed as close to the controller as possible; the datasheet classifies it as I/O, and the stated limit is VCC 5.5 V to 14 V in recommended operating conditions.
17 NC unconnected No electrical contact.
18 SW output Switching node of the buck regulator that connects to the bootstrap capacitor, the high-side NMOS source and the low-side NMOS drain through a short, low-inductance path.
19 HO output High-side NMOS gate drive output that connects to the high-side NMOS gate through a short, low-inductance path, with HO to SW limited to HB + 0.3 V.
20 HB power_in High-side driver supply for the bootstrap gate drive that connects to the bootstrap diode cathode and bootstrap capacitor, with HB to SW limited to 5.5 V to 14 V in recommended operating conditions.
21 NC unconnected No electrical contact.
22 VIN power_in Supply voltage input for the VCC regulator, rated 5.5 V to 65 V in recommended operating conditions.
23 NC unconnected No electrical contact.
24 UVLO input Undervoltage lockout programming pin where below 0.4 V the regulator shuts down, between 0.4 V and 1.25 V it stays in standby with no switching, and above 1.25 V soft-start and PWM gate drive are enabled, with a 20-μA source enabled above 1.25 V for hysteresis.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24-EP(4x4)
Category Power Supply Chip
Pins 25

CAD (KiCad official)

  • Symbol: LM5117PSQX
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.7x2.7mm
  • 3D model: WQFN-24-EP(4x4) (KiCad packages3D, STEP)
  • 3D model files: lm5117psqx-etched.step / lm5117psqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5117psqx.step / lm5117psqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (49 pp, sha256 9e27f24e84faebf5, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF