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LM5088MHX-1

Texas Instruments · DC-DC Converters · HTSSOP-16-EP

LM5088MHX-1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in Input supply voltage with an operating range of 4.5 V to 75 V.
2 EN input Below 0.4 V the regulator is in a low-power state, 0.4 V to 1.2 V selects standby mode, and above 1.2 V the controller is operational; a 5-µA pullup forces high when left open.
3 SS passive An internal 11-µA source charges the external capacitor to set the start-up rate, and the pin is held low in standby, VCC UV and thermal shutdown states.
4 RAMP passive An external capacitor between RAMP and GND sets the emulated current-mode ramp slope, with a recommended range of 100 pF to 2000 pF.
5 RT/SYNC input A single resistor to GND programs the oscillator from 50 kHz to 1 MHz, and an external sync signal higher in frequency can be applied through a small coupling capacitor while the RT resistor remains required.
6 GND power_in Ground return.
7 COMP output Output of the internal error amplifier, with the loop compensation network connected between COMP and FB.
8 FB input Inverting input of the internal error amplifier with a regulation threshold of 1.205 V.
9 OUT input Connect directly to the regulated output voltage.
10 DITH passive A capacitor to GND charged and discharged by 27-µA sources modulates the oscillator between -5% and +5% of nominal, and grounding the pin disables dithering.
11 CSG passive Low-side reference for the current sense resistor.
12 CS input Current measurement connection for the re-circulating diode that senses diode current at the end of the buck switch off time to provide the DC offset of the emulated ramp.
13 SW passive Connect to the source terminal of the external MOSFET switch.
14 HG output Connect to the gate terminal of the external MOSFET switch.
15 BOOT power_in An external bootstrap capacitor between BOOT and SW provides gate-driver bias and is charged from VCC through an internal diode during the buck off-time.
16 VCC power_out Bias regulator output that tracks VIN up to 7.8 V typical and requires a 0.1-µF to 10-µF ceramic decoupling capacitor, with an external 8.3 V to 13 V supply optionally applied to reduce dissipation.
17 EP passive Electrically isolated exposed pad that must be soldered to the ground plane to reduce thermal resistance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-16-EP
Category Power Management (PMIC)
Pins 17

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN voltage VIN 4.5 75 V 5
VCC voltage (externally supplied) VCC 8.3 13 V 5
Operation junction temperature TJ -40 125 °C 5
VIN, VOUT to GND VIN, VOUT 76 V to GND 5
BOOT to GND BOOT 90 V to GND 5
SW to GND SW -2 76 V to GND 5
VCC to GND VCC -0.3 16 V to GND 5
HG to SW HG -0.3 V to SW; max printed as BOOT + 0.3 V 5
EN to GND EN 14 V to GND 5
BOOT to SW BOOT -0.3 16 V to SW 5
CS, CSG to GND CS, CSG -0.3 0.3 V to GND 5
All other inputs to GND -0.3 7 V to GND 5
Junction temperature TJ 150 °C 5
Storage temperature Tstg -65 150 °C 5
VIN operating current IBIAS 5.5 mA VFB = 1.3 V, TJ = -40°C to +125°C 6
VIN standby current ISTANDBY 3.6 mA VEN = 1 V, TJ = -40°C to +125°C 6
VIN shutdown current ISHUTDOWN 26 µA VEN = 0 V, TJ = -40°C to +125°C 6
VCC regulation VVCC(Reg) 7.4 7.8 8.2 V VVCC = open 6
VCC sourcing current limit 30 mA VVCC = 0 6
EN shutdown threshold VEN 320 400 480 mV VEN rising 6
EN standby threshold VEN 1.1 1.2 1.3 V VEN rising 6
SS pullup current source ISS 8 11 13 µA VSS = 0 V 6
VREF FB reference voltage VREF 1.187 1.205 1.223 V Measured at FB pin; FB = COMP 6
FB input bias current IFB 18 100 nA VFB = 1.2 V 6
Forced HG off time tHG(OFF) 185 280 365 ns 6
Dithering range (fmin = fnom - 5%, fmax = fnom + 5%) fdither -5 5 % LM5088-1 dithering, relative to fnom 7
SYNC pulse width 15 150 ns 7
Cycle-by-cycle sense voltage threshold VCS(TH) 112 120 136 mV VRAMP = 0 V 7
RES threshold upper (rising) Vresup 1.1 1.2 1.3 V VCS = 0.125 V 7
RES threshold lower (falling) Vresdown 0.1 0.2 0.3 V 7
Charge source current Icharge 40 50 65 µA VCS ≥ 0.125 V 7
Discharge sink current Idischarge 20 27 34 µA VCS < 0.125 V 7
Discharge sink current (post fault) Irampdown 0.8 1.2 1.6 µA 7
RAMP current 1 IRAMP1 235 295 345 µA VVIN = 60 V, VOUT = 10 V 7
RAMP current 2 IRAMP2 18 25 30 µA VVIN = 10 V, VOUT = 10 V 7
HG low-state output voltage VOLH 115 215 mV IHG = 100 mA 7
VOUT bias current IVOUT 250 µA VOUT = 48 V 7
VCC undervoltage hysteresis 200 mV 6
EN shutdown hysteresis 100 mV VEN falling 6
EN standby hysteresis 120 mV VEN falling 6
EN pullup current source IEN 5 µA VEN = 0 V 6
FB to SS offset 150 mV VFB = 1.3 V 6
COMP sink and source current 3 mA 6
Minimum HG on time tON(MIN) 55 ns VVIN = 60 V 6
COMP to PWM comparator offset 930 mV 6
SYNC positive threshold 2.3 V 7
Cycle-by-cycle current limit delay 280 ns VRAMP = 2.5 V 7
Buck switch VDS protection 1.5 V VIN to SW 7
RAMP output low voltage 200 mV VVIN = 60 V, VOUT = 10 V 7
HG high-state output voltage VOHH 240 mV IHG = -100 mA, VOHH = VBOOT - VHG 7
HG rise time 12 ns Cload = 1000 pF 7
HG fall time 6 ns Cload = 1000 pF 7
Peak HG source current IOHH 1.5 A VHG = 0 V 7
Peak HG sink current IOLH 2 A VHG = VVCC 7
BOOT UVLO 3 V BOOT to SW 7
Pre-charge switch ON resistance RDS(ON) 72 Ω IVCC = 1 mA 7
Pre-charge switch on time 300 ns 7
Thermal shutdown temperature TSD 165 °C Junction temperature rising 7
Junction-to-ambient thermal resistance RθJA 40 °C/W PWP 16-pin package 6
Junction-to-case (bottom) thermal resistance RθJC(bot) 6 °C/W PWP 16-pin package 6

Materials and finish

As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).

Part Material Colour / plating Datasheet says Page
contacts copper power ground connections (CSS, RT, and CRAMP) directly to the regulator GND pin. Connect the GND pin and PGND pins together through to top-side copper area covering the entire underside of the device. 34

CAD (KiCad official)

  • Symbol: LM5088MHX-1
  • Footprint: Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)
  • 3D model files: lm5088mhx-1-etched.step / lm5088mhx-1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5088mhx-1.step / lm5088mhx-1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 471a76480f35dc1d, retrieved 2026-11-05, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF