component
LM5085SDE
Public Made by Adomby adom
Texas Instruments Global Sourcing Parts, WSON-8-EP(3x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5085SDE
Texas Instruments · Global Sourcing Parts · WSON-8-EP(3x3)
LM5085SDE from Texas Instruments, in a WSON-8-EP(3x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADJ | input | Current limit adjust: the current limit threshold is set by an external resistor from VIN to ADJ, together with the external sense resistor or the PFET RDS(ON). |
| 2 | RT | input | On-time control and shutdown: an external resistor from VIN to RT sets the buck switch on-time and switching frequency, and grounding this pin shuts down the controller; RT to GND is rated -0.3 V to 7 V. |
| 3 | FB | input | Voltage feedback from the regulated output to the regulation and over-voltage comparators, with a regulation level of 1.25 V; FB to GND is rated -0.3 V to 7 V. |
| 4 | GND | power_in | Circuit ground, the ground reference for all internal circuitry. |
| 5 | ISEN | input | Current sense input for current limit detection: connect to the PFET drain when using RDS(ON) sensing, or to the PFET source and the sense resistor when using an external sense resistor; ISEN to GND is rated -3 V to VIN + 0.3 V. |
| 6 | PGATE | output | Gate driver output that connects to the gate of the external PFET, swinging between VIN (Q1 off) and the VCC pin voltage (Q1 on). |
| 7 | VCC | power_out | Output of the negative voltage regulator (relative to VIN) that biases the PFET gate driver; a low ESR capacitor is required from VIN to VCC, placed as close as possible to the pins, and VIN to VCC is rated -0.3 V to 10 V. |
| 8 | VIN | power_in | Input supply voltage with an operating range of 4.5 V to 75 V; a low ESR bypass capacitor must be located as close as possible to the VIN and GND pins, and VIN to GND is rated -0.3 V to 76 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WSON-8-EP(3x3) |
| Category | Global Sourcing Parts |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
LM5085SDE - Footprint:
Package_SON:WSON-8-1EP_3x3mm_P0.5mm_EP1.6x2.0mm - 3D model: WSON-8-EP(3x3) (KiCad packages3D, STEP)
- 3D model files:
lm5085sde-etched.step/lm5085sde-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5085sde.step/lm5085sde.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
5a34a0aa7ad4c733, retrieved 2026-10-11, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).