component
LM5085QMYE
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Texas Instruments DC-DC Converters, MSOP-8-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LM5085QMYE
Texas Instruments · DC-DC Converters · MSOP-8-EP
LM5085QMYE from Texas Instruments, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADJ | input | The current limit threshold is set by an external resistor from VIN to ADJ, in conjunction with the external sense resistor or the PFET's RDS(ON). |
| 2 | RT | input | An external resistor from VIN to RT sets the buck switch on-time and switching frequency, and grounding this pin shuts down the controller. |
| 3 | FB | input | Voltage feedback input to the regulation and over-voltage comparators, with a regulated output level of 1.25 V. |
| 4 | GND | power_in | Circuit ground, the reference for all internal circuitry. |
| 5 | ISEN | input | Current sense input for current limit detection: connect to the PFET drain when using RDS(ON) sensing, or to the PFET source and the sense resistor when using an external sense resistor. |
| 6 | PGATE | output | Gate driver output that connects to the gate of the external PFET. |
| 7 | VCC | power_out | Output of the negative voltage regulator (relative to VIN) that biases the PFET gate driver; a low-ESR capacitor is required from VIN to VCC, placed as close as possible to the pins. |
| 8 | VIN | power_in | Input supply voltage with an operating range of 4.5 V to 75 V; a low-ESR bypass capacitor must be located as close as possible to the VIN and GND pins. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
LM5085QMYE - Footprint:
Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm - 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- 3D model files:
lm5085qmye-etched.step/lm5085qmye-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5085qmye.step/lm5085qmye.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
5a34a0aa7ad4c733, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM5085QMYE
**Texas Instruments** · DC-DC Converters · MSOP-8-EP
LM5085QMYE from Texas Instruments, in a MSOP-8-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | ADJ | input | The current limit threshold is set by an external resistor from VIN to ADJ, in conjunction with the external sense resistor or the PFET's RDS(ON). |
| 2 | RT | input | An external resistor from VIN to RT sets the buck switch on-time and switching frequency, and grounding this pin shuts down the controller. |
| 3 | FB | input | Voltage feedback input to the regulation and over-voltage comparators, with a regulated output level of 1.25 V. |
| 4 | GND | power_in | Circuit ground, the reference for all internal circuitry. |
| 5 | ISEN | input | Current sense input for current limit detection: connect to the PFET drain when using RDS(ON) sensing, or to the PFET source and the sense resistor when using an external sense resistor. |
| 6 | PGATE | output | Gate driver output that connects to the gate of the external PFET. |
| 7 | VCC | power_out | Output of the negative voltage regulator (relative to VIN) that biases the PFET gate driver; a low-ESR capacitor is required from VIN to VCC, placed as close as possible to the pins. |
| 8 | VIN | power_in | Input supply voltage with an operating range of 4.5 V to 75 V; a low-ESR bypass capacitor must be located as close as possible to the VIN and GND pins. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-8-EP |
| Category | Power Management (PMIC) |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `LM5085QMYE`
- Footprint: `Package_SO:MSOP-8-1EP_3x3mm_P0.65mm_EP1.5x1.8mm`
- 3D model: MSOP-8-EP (KiCad packages3D, STEP)
- 3D model files: `lm5085qmye-etched.step` / `lm5085qmye-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5085qmye.step` / `lm5085qmye.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5085-q1) (39 pp, sha256 `5a34a0aa7ad4c733`, retrieved 2026-10-08, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm5085qmye-datasheet.pdf)