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LM5072MHX-80
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Texas Instruments Power Over Ethernet (PoE) Controllers, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+53@@ -0,0 +1,53 @@+# LM5072MHX-80++**Texas Instruments** · Power Over Ethernet (PoE) Controllers · HTSSOP-16-EP++LM5072MHX-80 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | RT | passive | PWM controller oscillator frequency programming pin. |+| 2 | SS | passive | Soft-start programming pin. |+| 3 | VIN | power_in | Positive supply pin for the PD interface and the internal PWM controller start-up regulator. |+| 4 | RCLASS | passive | PD classification programming pin. |+| 5 | ICL_FAUX | bidirectional | Inrush current limit programming pin that also serves as the front auxiliary power enable pin. |+| 6 | DCCL | passive | PD interface DC current limit programming pin. |+| 7 | VEE | power_in | Negative supply pin for the PD interface, connected to the PoE and/or front auxiliary power return path. |+| 8 | RTN | power_in | PWM controller power return, connected to the drain of the internal PD interface hot swap MOSFET and to be externally connected to the PWM controller reference ground. |+| 9 | OUT | output | PWM controller gate driver output pin. |+| 10 | VCC | power_out | PWM controller start-up regulator output pin. |+| 11 | nPGOOD | output | PD interface Power Good indicator and delay timer pin, where an active low state indicates the PoE interface is in normal operation. |+| 12 | CS | input | PWM controller current sense input pin. |+| 13 | RAUX | input | Rear auxiliary power enable pin that can be programmed for auxiliary power dominance over PoE power. |+| 14 | FB | input | PWM controller voltage feedback pin and inverting input of the internal error amplifier; connect to ARTN to disable the error amplifier in isolated DC-DC converter applications. |+| 15 | COMP | bidirectional | Output of the internal error amplifier and control input to the PWM comparator, controlled by the secondary side error amplifier via an opto-coupler in isolated applications. |+| 16 | ARTN | power_in | PWM controller reference ground pin that should be shorted externally to RTN as a single point ground connection to improve noise immunity. |+| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-16-EP |+| Category | Power Management (PMIC) |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `LM5072MHX-80`+- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)+- 3D model files: `lm5072mhx-80-etched.step` / `lm5072mhx-80-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5072mhx-80.step` / `lm5072mhx-80.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5072) (37 pp, sha256 `2880e6942fe74392`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm5072mhx-80-datasheet.pdf)
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Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "lm5072mhx-80",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lm5072mhx-80.kicad_sym",+ "lm5072mhx-80.kicad_mod",+ "lm5072mhx-80.glb",+ "lm5072mhx-80.step",+ "lm5072mhx-80.lbr",+ "docs/hero.png",+ "docs/lm5072mhx-80-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lm5072mhx-80-hero.glb",+ "lm5072mhx-80-hero.overlay.json"+ ],+ "component": {+ "mpn": "LM5072MHX-80",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-16-EP",+ "pin_count": 17,+ "category": "Power Management (PMIC)",+ "subcategory": "Power Over Ethernet (PoE) Controllers",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lm5072",+ "parts": {+ "symbol": "lm5072mhx-80.kicad_sym",+ "footprint": "lm5072mhx-80.kicad_mod",+ "model_3d": "lm5072mhx-80-hero.glb",+ "model_3d_plain": "lm5072mhx-80.glb",+ "model_3d_step": "lm5072mhx-80-etched.step",+ "model_3d_step_plain": "lm5072mhx-80.step",+ "lbr": "lm5072mhx-80.lbr"+ },+ "distributor_links": {+ "lcsc": "C181411"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T03:53:43Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": null,+ "status": "no match"+ },+ "mouser": {+ "pn": null,+ "status": "no match"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "RT",+ "type": "passive",+ "description": "PWM controller oscillator frequency programming pin."+ },+ {+ "number": "2",+ "name": "SS",+ "type": "passive",+ "description": "Soft-start programming pin."+ },+ {+ "number": "3",+ "name": "VIN",+ "type": "power_in",+ "description": "Positive supply pin for the PD interface and the internal PWM controller start-up regulator."+ },+ {+ "number": "4",+ "name": "RCLASS",+ "type": "passive",+ "description": "PD classification programming pin."+ },+ {+ "number": "5",+ "name": "ICL_FAUX",+ "type": "bidirectional",+ "description": "Inrush current limit programming pin that also serves as the front auxiliary power enable pin."+ },+ {+ "number": "6",+ "name": "DCCL",+ "type": "passive",+ "description": "PD interface DC current limit programming pin."+ },+ {+ "number": "7",+ "name": "VEE",+ "type": "power_in",+ "description": "Negative supply pin for the PD interface, connected to the PoE and/or front auxiliary power return path."+ },+ {+ "number": "8",+ "name": "RTN",+ "type": "power_in",+ "description": "PWM controller power return, connected to the drain of the internal PD interface hot swap MOSFET and to be externally connected to the PWM controller reference ground."+ },+ {+ "number": "9",+ "name": "OUT",+ "type": "output",+ "description": "PWM controller gate driver output pin."+ },+ {+ "number": "10",+ "name": "VCC",+ "type": "power_out",+ "description": "PWM controller start-up regulator output pin."+ },+ {+ "number": "11",+ "name": "nPGOOD",+ "type": "output",+ "description": "PD interface Power Good indicator and delay timer pin, where an active low state indicates the PoE interface is in normal operation."+ },+ {+ "number": "12",+ "name": "CS",+ "type": "input",+ "description": "PWM controller current sense input pin."+ },+ {+ "number": "13",+ "name": "RAUX",+ "type": "input",+ "description": "Rear auxiliary power enable pin that can be programmed for auxiliary power dominance over PoE power."+ },+ {+ "number": "14",+ "name": "FB",+ "type": "input",+ "description": "PWM controller voltage feedback pin and inverting input of the internal error amplifier; connect to ARTN to disable the error amplifier in isolated DC-DC converter applications."+ },+ {+ "number": "15",+ "name": "COMP",+ "type": "bidirectional",+ "description": "Output of the internal error amplifier and control input to the PWM comparator, controlled by the secondary side error amplifier via an opto-coupler in isolated applications."+ },+ {+ "number": "16",+ "name": "ARTN",+ "type": "power_in",+ "description": "PWM controller reference ground pin that should be shorted externally to RTN as a single point ground connection to improve noise immunity."+ },+ {+ "number": "17",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin list taken from the pin description table on page 3 and cross-checked against the TSSOP-16 EP co; KiCad ERC types for RT, SS, RCLASS, DCCL, and EP are inferred as passive because the datasheet does ; Datasheet is a 7-of-37-page excerpt; the package addendum on page 29 confirms LM5072MHX-80/NOPB is a",+ "exposed pad 17 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 7,+ "cost_usd": 0.0536,+ "at": "2026-10-08T03:53:24"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm5072",+ "pages": 37,+ "sha256": "2880e6942fe74392",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm5072mhx-80.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7982746831c0bd23f4690608869ad67776faae5c762fb0376666126a3998921b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm5072mhx-80-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "d16c3aa546abe4149c585dc2d4a423c99cf895ba16904b3dfbbce77c860e4ee0",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}