main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lm5071mtx-80: viewers · Ray 1d ago
lm5071mtx-80-etched.glb lm5071mtx-80: factory component page (tier=lcsc) · Ray 1d ago
lm5071mtx-80-etched.step lm5071mtx-80: factory component page (tier=lcsc) · Ray 1d ago
lm5071mtx-80-hero.glb lm5071mtx-80: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lm5071mtx-80-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lm5071mtx-80.glb Publish 0.1.0 · Ray 1d ago
lm5071mtx-80.kicad_mod Publish 0.1.0 · Ray 1d ago
lm5071mtx-80.kicad_sym Publish 0.1.0 · Ray 1d ago
lm5071mtx-80.lbr Publish 0.1.0 · Ray 1d ago
lm5071mtx-80.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Initial commit: component/lm5071mtx-80 · Ray 1d ago

LM5071MTX-80

Texas Instruments · Power Over Ethernet (PoE) Controllers · TSSOP-16

LM5071MTX-80 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VIN power_in System high potential input, the diode-OR of the lines entering the PD and the more positive input potential; operating VIN range is 1.8V to 60V and absolute maximum VIN to VEE is 80V.
2 RSIG passive Signature resistor connection; a resistor from VIN to this pin sets signature detection and sits in parallel with the UVLO resistors, with RSIG to VIN rated -12V to 0V.
3 RCLASS passive Classification resistor connection; the classification programming resistor connects from this pin to VEE, with RCLASS to VEE rated -0.3V to 7V.
4 AUX input Auxiliary input startup pin; a resistor divider from the AUX voltage to VEE sets startup levels against a 2.5V threshold, with AUX to VEE rated -0.3V to 57V and an internal pull-down above 300kΩ when open.
5 UVLO input Line undervoltage lockout input; an external divider from VIN to UVLORTN sets shutdown levels against a 2.00V threshold, with hysteresis from a switched 10uA internal current source and UVLO to VEE rated -0.3V to 13V.
6 UVLORTN passive Return for the external UVLO resistor divider, connected to the bottom resistor of the divider between the UVLO pin and this pin.
7 VEE power_in System low potential input, the diode-OR of the RJ45 connector and PSE -48V supply and the more negative input potential.
8 RTN power_in System return for the PWM converter, being the drain of the internal current-limiting power MOSFET that connects VEE to the DC-DC converter return path; RTN to VEE is rated -0.3V to 80V.
9 OUT output PWM controller output driving the DC-DC converter gate with 800mA peak sink current capability, with OUT to ARTN rated -0.3V to 16V.
10 VCC power_out Output of the internal high-voltage series pass regulator, nominally 7.8V, which shuts down when an auxiliary winding raises the voltage above the set point; an external voltage of 8.1V to 15V may be applied, with VCC to ARTN rated -0.3V to 16V.
11 FB input Feedback signal and inverting input of the internal error amplifier, whose non-inverting input is tied to a 1.25V reference; all other inputs to ARTN are rated -0.3V to 7V.
12 COMP output Output of the error amplifier feeding the PWM modulator, with an internal 5kΩ pull-up available to bias an opto-coupler transistor.
13 CS input Current sense input for current-mode control and overcurrent protection, where OUT switches low for cycle-by-cycle limiting when CS exceeds 0.5V and CS is blanked for 50ns after OUT goes high.
14 RT / SYNC input Oscillator timing resistor connection from RT to ARTN that sets the switching frequency, and synchronization input that accepts narrow AC-coupled pulses from an external clock.
15 SS passive Soft-start input where an external capacitor and an internal 10uA current source set the soft-start ramp rate.
16 ARTN power_in Analog PWM supply return for sensitive analog circuitry including the SMPS current limit amplifier, with ARTN to RTN rated -0.3V to 0.3V.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package TSSOP-16
Category Power Management (PMIC)
Pins 16

CAD (KiCad official)

  • Symbol: LM5071MTX-80
  • Footprint: Package_SO:TSSOP-16_4.4x5mm_P0.65mm
  • 3D model: TSSOP-16 (KiCad packages3D, STEP)
  • 3D model files: lm5071mtx-80-etched.step / lm5071mtx-80-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5071mtx-80.step / lm5071mtx-80.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (27 pp, sha256 4e573906dfea5690, retrieved 2026-10-08, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF