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LM5071MTX-80
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Texas Instruments Power Over Ethernet (PoE) Controllers, TSSOP-16. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+52@@ -0,0 +1,52 @@+# LM5071MTX-80++**Texas Instruments** · Power Over Ethernet (PoE) Controllers · TSSOP-16++LM5071MTX-80 from Texas Instruments, in a TSSOP-16. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | VIN | power_in | System high potential input, the diode-OR of the lines entering the PD and the more positive input potential; operating VIN range is 1.8V to 60V and absolute maximum VIN to VEE is 80V. |+| 2 | RSIG | passive | Signature resistor connection; a resistor from VIN to this pin sets signature detection and sits in parallel with the UVLO resistors, with RSIG to VIN rated -12V to 0V. |+| 3 | RCLASS | passive | Classification resistor connection; the classification programming resistor connects from this pin to VEE, with RCLASS to VEE rated -0.3V to 7V. |+| 4 | AUX | input | Auxiliary input startup pin; a resistor divider from the AUX voltage to VEE sets startup levels against a 2.5V threshold, with AUX to VEE rated -0.3V to 57V and an internal pull-down above 300kΩ when open. |+| 5 | UVLO | input | Line undervoltage lockout input; an external divider from VIN to UVLORTN sets shutdown levels against a 2.00V threshold, with hysteresis from a switched 10uA internal current source and UVLO to VEE rated -0.3V to 13V. |+| 6 | UVLORTN | passive | Return for the external UVLO resistor divider, connected to the bottom resistor of the divider between the UVLO pin and this pin. |+| 7 | VEE | power_in | System low potential input, the diode-OR of the RJ45 connector and PSE -48V supply and the more negative input potential. |+| 8 | RTN | power_in | System return for the PWM converter, being the drain of the internal current-limiting power MOSFET that connects VEE to the DC-DC converter return path; RTN to VEE is rated -0.3V to 80V. |+| 9 | OUT | output | PWM controller output driving the DC-DC converter gate with 800mA peak sink current capability, with OUT to ARTN rated -0.3V to 16V. |+| 10 | VCC | power_out | Output of the internal high-voltage series pass regulator, nominally 7.8V, which shuts down when an auxiliary winding raises the voltage above the set point; an external voltage of 8.1V to 15V may be applied, with VCC to ARTN rated -0.3V to 16V. |+| 11 | FB | input | Feedback signal and inverting input of the internal error amplifier, whose non-inverting input is tied to a 1.25V reference; all other inputs to ARTN are rated -0.3V to 7V. |+| 12 | COMP | output | Output of the error amplifier feeding the PWM modulator, with an internal 5kΩ pull-up available to bias an opto-coupler transistor. |+| 13 | CS | input | Current sense input for current-mode control and overcurrent protection, where OUT switches low for cycle-by-cycle limiting when CS exceeds 0.5V and CS is blanked for 50ns after OUT goes high. |+| 14 | RT / SYNC | input | Oscillator timing resistor connection from RT to ARTN that sets the switching frequency, and synchronization input that accepts narrow AC-coupled pulses from an external clock. |+| 15 | SS | passive | Soft-start input where an external capacitor and an internal 10uA current source set the soft-start ramp rate. |+| 16 | ARTN | power_in | Analog PWM supply return for sensitive analog circuitry including the SMPS current limit amplifier, with ARTN to RTN rated -0.3V to 0.3V. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | TSSOP-16 |+| Category | Power Management (PMIC) |+| Pins | 16 |++## CAD (KiCad official)++- Symbol: `LM5071MTX-80`+- Footprint: `Package_SO:TSSOP-16_4.4x5mm_P0.65mm`+- 3D model: TSSOP-16 (KiCad packages3D, STEP)+- 3D model files: `lm5071mtx-80-etched.step` / `lm5071mtx-80-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5071mtx-80.step` / `lm5071mtx-80.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5071) (27 pp, sha256 `4e573906dfea5690`, retrieved 2026-10-08, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm5071mtx-80-datasheet.pdf)
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operating VIN range is 1.8V to 60V and absolute maximum VIN to VEE is 80V."+ },+ {+ "number": "2",+ "name": "RSIG",+ "type": "passive",+ "description": "Signature resistor connection; a resistor from VIN to this pin sets signature detection and sits in parallel with the UVLO resistors, with RSIG to VIN rated -12V to 0V."+ },+ {+ "number": "3",+ "name": "RCLASS",+ "type": "passive",+ "description": "Classification resistor connection; the classification programming resistor connects from this pin to VEE, with RCLASS to VEE rated -0.3V to 7V."+ },+ {+ "number": "4",+ "name": "AUX",+ "type": "input",+ "description": "Auxiliary input startup pin; a resistor divider from the AUX voltage to VEE sets startup levels against a 2.5V threshold, with AUX to VEE rated -0.3V to 57V and an internal pull-down above 300kΩ when open."+ },+ {+ "number": "5",+ "name": "UVLO",+ "type": "input",+ "description": "Line undervoltage lockout input; an external divider from VIN to UVLORTN sets shutdown levels against a 2.00V threshold, with hysteresis from a switched 10uA internal current source and UVLO to VEE rated -0.3V to 13V."+ },+ {+ "number": "6",+ "name": "UVLORTN",+ "type": "passive",+ "description": "Return for the external UVLO resistor divider, connected to the bottom resistor of the divider between the UVLO pin and this pin."+ },+ {+ "number": "7",+ "name": "VEE",+ "type": "power_in",+ "description": "System low potential input, the diode-OR of the RJ45 connector and PSE -48V supply and the more negative input potential."+ },+ {+ "number": "8",+ "name": "RTN",+ "type": "power_in",+ "description": "System return for the PWM converter, being the drain of the internal current-limiting power MOSFET that connects VEE to the DC-DC converter return path; RTN to VEE is rated -0.3V to 80V."+ },+ {+ "number": "9",+ "name": "OUT",+ "type": "output",+ "description": "PWM controller output driving the DC-DC converter gate with 800mA peak sink current capability, with OUT to ARTN rated -0.3V to 16V."+ },+ {+ "number": "10",+ "name": "VCC",+ "type": "power_out",+ "description": "Output of the internal high-voltage series pass regulator, nominally 7.8V, which shuts down when an auxiliary winding raises the voltage above the set point; an external voltage of 8.1V to 15V may be applied, with VCC to ARTN rated -0.3V to 16V."+ },+ {+ "number": "11",+ "name": "FB",+ "type": "input",+ "description": "Feedback signal and inverting input of the internal error amplifier, whose non-inverting input is tied to a 1.25V reference; all other inputs to ARTN are rated -0.3V to 7V."+ },+ {+ "number": "12",+ "name": "COMP",+ "type": "output",+ "description": "Output of the error amplifier feeding the PWM modulator, with an internal 5kΩ pull-up available to bias an opto-coupler transistor."+ },+ {+ "number": "13",+ "name": "CS",+ "type": "input",+ "description": "Current sense input for current-mode control and overcurrent protection, where OUT switches low for cycle-by-cycle limiting when CS exceeds 0.5V and CS is blanked for 50ns after OUT goes high."+ },+ {+ "number": "14",+ "name": "RT / SYNC",+ "type": "input",+ "description": "Oscillator timing resistor connection from RT to ARTN that sets the switching frequency, and synchronization input that accepts narrow AC-coupled pulses from an external clock."+ },+ {+ "number": "15",+ "name": "SS",+ "type": "passive",+ "description": "Soft-start input where an external capacitor and an internal 10uA current source set the soft-start ramp rate."+ },+ {+ "number": "16",+ "name": "ARTN",+ "type": "power_in",+ "description": "Analog PWM supply return for sensitive analog circuitry including the SMPS current limit amplifier, with ARTN to RTN rated -0.3V to 0.3V."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: Pin numbers and names were taken from the Pin Descriptions table on page 3 (text). The page 2 connec; VCC is described as the output of the internal series pass regulator (power_out) but the operating r; Types for RSIG, RCLASS, UVLORTN, and SS were set to passive because they are resistor or capacitor c"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0525,+ "at": "2026-10-08T18:50:01"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm5071",+ "pages": 27,+ "sha256": "4e573906dfea5690",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 16,+ "described": 16,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm5071mtx-80.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "6ad5e98224d02a427d9a6b929a28dbc158b9925fba5adec12db05079f1016948",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm5071mtx-80-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "3672b66787a94229c2f7423cce4a8b5a25214e8133299b74cedbf268238c32e6",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}