component
LM5069MMX-2
Public Made by Adomby adom
Texas Instruments Surge Protection Devices (SPDs), VSSOP-10-0.5mm. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5069MMX-2
Texas Instruments · Surge Protection Devices (SPDs) · VSSOP-10-0.5mm
LM5069MMX-2 from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE | input | Current sense input: the voltage across the current sense resistor RS is measured from VIN to this pin, and if it reaches 55 mV the load current is limited and the fault timer activates. |
| 2 | VIN | power_in | Positive supply input (9 V to 80 V recommended operating range); a small ceramic bypass capacitor close to this pin is recommended to suppress transients that occur when the load current is switched off. |
| 3 | UVLO | input | Undervoltage lockout: an external resistor divider from the system input sets the undervoltage turn-on threshold, an internal 21-µA source provides hysteresis, the enable threshold at the pin is 2.5 V, and the pin can also be used for remote shutdown. |
| 4 | OVLO | input | Overvoltage lockout: an external resistor divider from the system input sets the overvoltage turn-off threshold, an internal 21-µA source provides hysteresis, and the disable threshold at the pin is 2.5 V. |
| 5 | GND | power_in | Circuit ground. |
| 6 | TIMER | bidirectional | Timing capacitor: an external capacitor on this pin sets the insertion time delay and the fault timeout period, and also sets the restart timing of the LM5069-2. |
| 7 | PWR | input | Power limit set: an external resistor on this pin, together with the current sense resistor RS, sets the maximum power dissipation allowed in the external series pass MOSFET. |
| 8 | PGD | output | Power Good indicator, an open-drain output: it is active (high) when the external MOSFET VDS decreases below 1.25 V and switches low when VDS increases above 2.5 V. |
| 9 | OUT | input | Output feedback: connect to the output rail (external MOSFET source), used internally to determine MOSFET VDS for power limiting and to control the PGD indicator. |
| 10 | GATE | output | Gate drive output: connect to the external MOSFET gate; the pin voltage is typically 12 V above the OUT pin when enabled. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VSSOP-10-0.5mm |
| Category | Circuit Protection |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
LM5069MMX-2 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
- 3D model files:
lm5069mmx-2-etched.step/lm5069mmx-2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5069mmx-2.step/lm5069mmx-2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (39 pp, sha256
202f4b206d6b8f28, retrieved 2026-10-08, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).