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LM5066IPMHE

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Texas Instruments Monitors & Reset Circuits, HTSSOP-28-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LM5066IPMHE

Texas Instruments · Monitors & Reset Circuits · HTSSOP-28-EP

LM5066IPMHE from Texas Instruments, in a HTSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT input Output feedback; connect to the output rail (external MOSFET source), used internally to determine MOSFET VDS for power limiting and to monitor the output voltage.
2 GATE output Gate drive output; connect to the external MOSFET's gate.
3 SENSE input Current sense input; the voltage across RSNS is measured from VIN_K to this pin, and if it reaches the overcurrent threshold the load current is limited and the fault timer activates.
4 VIN_K input Positive supply Kelvin pin on which the input voltage is measured.
5 VIN power_in Positive supply input connection for the device, operating range 10 V to 80 V.
6 NC unconnected No connection.
7 UVLO/EN input Undervoltage lockout set by an external resistor divider with enable threshold nominally 2.48 V and 20-µA hysteresis current source; also usable for remote shutdown.
8 OVLO input Overvoltage lockout set by an external resistor divider with disable threshold of 2.46 V and 21-µA hysteresis current source.
9 AGND power_in Analog device ground; connect to GND at the pin.
10 GND power_in Circuit ground.
11 SDAI input SMBus data input; connect to SDAO if the application does not require unidirectional isolation devices.
12 SDAO output SMBus data output; connect to SDAI if the application does not require unidirectional isolation devices.
13 SCL input SMBus clock pin.
14 SMBA output SMBus alert pin, active low.
15 VREF power_in Internally generated precision reference for analog-to-digital conversion; bypass with a 1-µF capacitor to ground.
16 DIODE passive Connect to a diode-configured MMBT3904 NPN transistor for temperature monitoring; ground if unused.
17 VAUX input Auxiliary voltage input for telemetry from an external source, full-scale input of 2.97 V.
18 ADR2 input Tri-state SMBus address line 2; connect to GND, VDD, or leave floating.
19 ADR1 input Tri-state SMBus address line 1; connect to GND, VDD, or leave floating.
20 ADR0 input Tri-state SMBus address line 0; connect to GND, VDD, or leave floating.
21 VDD power_out Internally sub-regulated 4.85-V bias supply, current limited to 30 mA; bypass with a 1-µF capacitor to ground.
22 CL input Current limit range; GND or floating sets the nominal threshold at 50 mV, connecting to VDD sets it to 26 mV.
23 FB input Power good feedback; external resistor divider from the output sets the PGD switching voltage, threshold nominally 2.46 V with 20-µA hysteresis current.
24 RETRY input Fault retry input; GND or floating makes the device continually retry power-up during a fault, VDD makes it latch off during a fault.
25 TIMER passive External capacitor sets insertion time delay, fault timeout period, and restart timing.
26 PWR passive Power limit set; an external resistor with RSNS sets the maximum power dissipation allowed in the external series pass MOSFET.
27 NC unconnected No connection.
28 PGD output Open-drain power good indicator, high when FB is above 2.46 V and the input supply is within UV and OV thresholds; capable of sustaining 80 V off-state.
29 EP power_in Exposed pad; solder to the ground plane to reduce thermal resistance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-28-EP
Category Power Management ICs
Pins 29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature Tstg -65 150 °C 5
ESD HBM, all pins except GATE VESD -2 2 kV Human body model, ANSI/ESDA/JEDEC JS-001 5
ESD CDM, all pins VESD -500 500 V JESD22-C101 5
VIN, SENSE, OUT voltage 10 80 V 5
Junction temperature TJ -40 125 °C 5
Junction-to-ambient thermal resistance RθJA 35.6 °C/W PWP 28 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 19.9 °C/W PWP 28 pins 5
Junction-to-board thermal resistance RθJB 16.8 °C/W PWP 28 pins 5
Junction-to-case (bottom) thermal resistance RθJC(bot) 2.9 °C/W PWP 28 pins 5
Input current, enabled IIN-EN 5.6 7 mA VUVLO = 3 V and VOVLO = 2 V 6
POR threshold to trigger insertion timer PORIT 7.8 9 V VVIN increasing 6
POR threshold to enable all functions POREN 8.6 9.9 V VVIN increasing 6
POREN hysteresis PORHYS 100 mV VVIN decreasing 6
VDD voltage VDD 4.6 4.9 5.15 V IVDD = 0 mA 6
VDD voltage VDD 4.6 4.85 5.15 V IVDD = 10 mA 6
VDD current limit VDDILIM -50 -30 -15 mA 6
VDD reset threshold VDDPOR 4.1 V VVDD rising 6
UVLO threshold UVLOTH 2.41 2.48 2.55 V VUVLO falling 6
UVLO hysteresis current UVLOHYS 16 20 24 µA VUVLO = 1 V 6
UVLO bias current UVLOBIAS 1 µA VUVLO = 3 V 6
OVLO threshold OVLOTH 2.39 2.46 2.53 V VOVLO rising 6
OVLO hysteresis current OVLOHYS -24 -21 -16 µA VOVLO = 1 V 6
OVLO bias current OVLOBIAS 1 µA VOVLO = 1 V 6
PGD output low voltage PGDVOL 100 400 mV ISINK = 2 mA 6
PGD off leakage current PGDIOH 1 µA VPGD = 80 V 6
FB threshold FBTH 2.41 2.46 2.52 V VUVLO = 3 V and VOVLO = 2 V 6
FB hysteresis current FBHYS -25 -20 -15 µA 6
FB off leakage current FBLEAK 1 µA VFB = 2.3 V 6
Power limit sense voltage VVIN_K, VSENSE 7.4 9.4 11.4 mV VSENSE, VOUT = 48 V, RPWR = 60 kΩ 6
Power limit sense voltage VVIN_K, VSENSE 1.5 3.5 5.7 mV VSENSE, VOUT = 48 V, RPWR = 20 kΩ 6
Power limit sense voltage VVIN_K, VSENSE 1.85 3.5 5.02 mV VSENSE, VOUT = 48 V, RPWR = 20 kΩ, TJ = 0°C to 85°C 6
Power limit sense voltage VVIN_K, VSENSE 15 18.75 22.5 mV VSENSE, VOUT = 24 V, RPWR = 60 kΩ 6
Power limit sense voltage VVIN_K, VSENSE 5 7.23 10 mV VSENSE, VOUT = 24 V, RPWR = 20 kΩ 6
PWR pin current IPWR -20 µA VPWR = 2.5 V 6
PWR pin impedance when disabled RSAT(PWR) 120 Ω VUVLO = 2 V 6
GATE source current IGATE -40 -20 -7.5 µA Normal operation 6
GATE fault sink current IGATE 3.4 4.2 5.3 mA VUVLO = 2 V 6
GATE POR/circuit breaker sink current IGATE 90 160 230 mA VVIN_K, VSENSE = 60 mV or VVIN < PORIT, VGATE = 5 V, OUT = 0 V, CB/CL ratio bit = 0, CL = 1 6
GATE to OUT Zener reverse-bias voltage VGATEZ 15 16.5 18 V VGATE, VOUT, IZ = -100 µA 6
Peak charge pump voltage VGATECP 11 13 15 V VGATE, VOUT (VIN = VOUT) 6
OUT bias current, enabled IOUT-EN 60 80 100 µA VIN = VOUT, normal operation 6
OUT bias current, disabled IOUT-DIS -65 -50 -35 µA Disabled, OUT = 0 V, VVIN_K = VSENSE 6
Current limit threshold voltage VCL 23.4 26 28.6 mV CL = VDD 7
Current limit threshold voltage VCL 45 50 55 mV CL = GND 7
SENSE input current ISENSE 20 25 35 µA Enabled, SENSE = OUT 7
SENSE input current ISENSE 190 220 250 µA Enabled, OUT = 0 V 7
Circuit breaker to current limit ratio RTCB 1.64 1.94 2.23 V/V CB/CL ratio bit = 0, ILIM = 50 mV 7
Circuit breaker to current limit ratio RTCB 3.28 3.87 4.45 V/V CB/CL ratio bit = 1, ILIM = 50 mV 7
Circuit breaker to current limit ratio RTCB 1.5 1.88 2.3 V/V CB/CL ratio bit = 0, ILIM = 26 mV 7
Circuit breaker to current limit ratio RTCB 3.1 3.75 4.45 V/V CB/CL ratio bit = 1, ILIM = 26 mV 7
Circuit breaker threshold voltage VCB 76 96 116 mV CB/CL ratio bit = 0, ILIM = 50 mV 7
Circuit breaker threshold voltage VCB 155 193 235 mV CB/CL ratio bit = 1, ILIM = 50 mV 7
Circuit breaker threshold voltage VCB 38 48 58 mV CB/CL ratio bit = 0, ILIM = 26 mV 7
TIMER upper threshold VTMRH 3.74 3.9 4.07 V 7
TIMER lower threshold, restart cycles VTMRL 1 1.2 1.4 V Restart cycles 7
TIMER insertion time current ITIMER -5.9 -4.8 -3.3 µA Insertion time current 7
TIMER sink current, end of insertion time ITIMER 0.9 1.5 2.1 mA End of insertion time 7
TIMER fault detection current ITIMER -90 -75 -60 µA TIMER pin = 2 V 7
TIMER fault sink current ITIMER 1.7 2.5 3.2 µA Fault sink current 7
Reference voltage VREF 2.93 2.97 3.02 V 7
Input voltage full-scale range VINFSR 86 88.9 91 V 7
Input current absolute accuracy IINACC -1.75 1.75 % VVIN_K, VSENSE = 22 mV (80% IINFSR), CL = VDD 7
VIN, VOUT absolute accuracy VACC -1.25 1.25 % VVIN, VVOUT = 48, 80 V 8

CAD (KiCad official)

  • Symbol: LM5066IPMHE
  • Footprint: Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm
  • 3D model: HTSSOP-28-EP (KiCad packages3D, STEP)
  • 3D model files: lm5066ipmhe-etched.step / lm5066ipmhe-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5066ipmhe.step / lm5066ipmhe.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (70 pp, sha256 1c957c735de35462, retrieved 2026-10-23, tier: manufacturer)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF