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Contents

README

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LM5060Q1MMX

Texas Instruments · Global Sourcing Parts · VSSOP-10-0.5mm

LM5060Q1MMX from Texas Instruments, in a VSSOP-10-0.5mm. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SENSE input Input voltage sense pin where a 16 µA typical constant current sink flows through an external resistor to set the VDS fault detection threshold.
2 VIN power_in Supply voltage input with an operating range of 5.5 V to 65 V, where the internal power-on-reset typically becomes active above 5.1 V and a small ceramic bypass capacitor close to the pin is recommended.
3 OVP input Over-voltage protection comparator input set by an external resistor divider; GATE is pulled low when OVP exceeds the typical 2.0 V threshold without latching off, and operation resumes when OVP falls below typically 1.76 V.
4 UVLO input Under-voltage lockout comparator input set by a resistor divider from input supply to ground; above typically 1.6 V it releases the GATE pull-down, and a 5.5 µA typical sink holds it low when open.
5 EN input Enable input where a voltage below 0.8 V switches the device to low-current shutdown and above 2.0 V enables the internal bias and UVLO comparator, with a 6 µA typical sink holding it low when open.
6 GND power_in Circuit ground.
7 TIMER bidirectional Timing capacitor pin that sets the VDS fault detection delay; when the TIMER pin exceeds the 2.0 V threshold the MOSFET is latched off until EN, UVLO or VIN is toggled low and then high.
8 nPGD output Open-drain fault status output that is active when the OUT pin voltage exceeds the SENSE pin voltage, with low indicating no fault per the pin table.
9 OUT input Output voltage sense connected to the external MOSFET source, used internally to detect VDS and VGS conditions.
10 GATE output Gate drive output for the external N-channel MOSFET, charged by a 24 µA typical charge-pump source and clamped by an internal zener at typically 16.8 V above OUT, with an optional capacitor to GND to slow dV/dt.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VSSOP-10-0.5mm
Category Global Sourcing Parts
Pins 10

CAD (KiCad official)

  • Symbol: LM5060Q1MMX
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: VSSOP-10-0.5mm (KiCad packages3D, STEP)
  • 3D model files: lm5060q1mmx-etched.step / lm5060q1mmx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5060q1mmx.step / lm5060q1mmx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (41 pp, sha256 38a3fbe1f0f97004, retrieved 2026-10-11, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF