component
LM5051MAE
Public Made by Adomby adom
Texas Instruments Power Distribution Switches, SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 1d ago |
| viewers | 1d ago |
| lm5051mae-etched.glb | 1d ago |
| lm5051mae-etched.step | 1d ago |
| lm5051mae-hero.glb | 1d ago |
| lm5051mae-hero.overlay.json | 1d ago |
| lm5051mae.glb | 1d ago |
| lm5051mae.kicad_mod | 1d ago |
| lm5051mae.kicad_sym | 1d ago |
| lm5051mae.lbr | 1d ago |
| lm5051mae.step | 1d ago |
| package.json | 1d ago |
| page.json | 1d ago |
| README.md | 1d ago |
| verification.json | 1d ago |
LM5051MAE
Texas Instruments · Power Distribution Switches · SOIC-8
LM5051MAE from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | LINE | power_in | Power supply pin that biases the internal 12V zener shunt regulator through an internal 50 kΩ typical series resistor, with a 36V to 100V operating voltage range. |
| 2 | VCC | power_out | Connection to the internal 12V zener shunt regulator that must be bypassed with a minimum 0.1µF capacitor to VSS, with a recommended bias current of 1 mA minimum and 10 mA maximum. |
| 3 | OFF | input | FET Test Mode control input where a logic high pulls the GATE pin low to turn off the external MOSFET, with an operating voltage of 0.0V to 5.0V and no more than 5.5V above INP/VSS. |
| 4 | nFGD | output | Open drain FET test output that goes active low when the MOSFET forward voltage is greater than 260 mV typical, requires a pull-up not higher than VSS + 5.5V, and should not sink more than 2 mA. |
| 5 | INP/VSS | power_in | Internally connected to device pin 7; it should be externally connected to pin 7 at the package, with no current flowing through the internal connection between pins 5 and 7. |
| 6 | INN | input | Voltage sense connection to the external MOSFET drain, with an operating range of -1V to 100V relative to INP/VSS and an absolute maximum of -2V to 103V. |
| 7 | INP/VSS | power_in | Negative supply voltage connection and common MOSFET source connection to which all device voltages and currents are referenced unless otherwise stated. |
| 8 | GATE | output | Connection to the external MOSFET gate, which has limited built-in ESD protection and requires the leads to be shorted together or the device placed in conductive foam during handling. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Power Management (PMIC) |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| LINE Pin to INP/VSS voltage | -0.3 | 103 | V | 3 | |||
| INN Pin to INP/VSS voltage | -2 | 103 | V | 3 | |||
| OFF Pin to INP/VSS voltage | -0.3 | 7 | V | 3 | |||
| VCC Pin Sink to INP/VSS current | -0.1 | 20 | mA | 3 | |||
| nFGD Pin to INP/VSS voltage (Off) | -0.3 | 7 | V | Off | 3 | ||
| Storage Temperature Range | -65 | 150 | °C | 3 | |||
| ESD (HBM) | -2 | 2 | kV | Human Body Model | 3 | ||
| Peak Reflow Temperature | 260 | °C | 30 sec | 3 | |||
| LINE Pin Voltage | 36 | 100 | V | Relative to VSS pin | 3 | ||
| INN Pin Voltage | -1 | 100 | V | Relative to VSS pin | 3 | ||
| VCC Pin Current | 1 | 10 | mA | 3 | |||
| OFF Pin Voltage | 0 | 5 | V | 3 | |||
| nFGD Voltage (Off) | 0 | 5 | V | 3 | |||
| nFGD Sink Current (On) | 0 | 2 | mA | 3 | |||
| Junction Temperature Range (TJ) | TJ | -40 | 125 | °C | 3 | ||
| LINE Pin current | ILINE | 690 | 780 | μA | VLINE = 48.0V, VCC Pin = Open | 4 | |
| VCC Operating Voltage Range | 4.5 | V | LINE Pin = Open | 4 | |||
| VCC Shunt Zener Voltage | VZ | 11.9 | 13 | 14.3 | V | IVCC = 2 mA | 4 |
| VCC Shunt Zener Voltage | VZ | 12.5 | 13.5 | 14.5 | V | IVCC = 10 mA | 4 |
| Shunt Zener Regulation | ΔVZ | 0.5 | 1.11 | V | IVCC = 2 mA to 10 mA | 4 | |
| Supply Current | IVCC | 1 | 1.5 | mA | VVCC = VZ - 100mV | 4 | |
| Supply Current | IVCC | 0.4 | 1.1 | mA | VVCC = 5.0V | 4 | |
| GATE Charge Current | IGATE | 0.28 | 0.66 | 0.95 | mA | VGATE = 5.5V, VINN = -150mV | 4 |
| GATE Discharge Current | IGATE | 2.4 | 3.5 | A | VGATE = 5.5V, VINN = -150 mV to +300 mV, t ≤ 10 ms | 4 | |
| GATE Pin High Voltage | VGATE | 9.98 | 10.2 | V | VVCC = 10.25V, LINE = Open | 4 | |
| GATE Pin High Voltage | VGATE | 4.7 | 4.95 | V | VVCC = 5.0V, LINE = Open | 4 | |
| Reverse Threshold | VSD(REV) | -112.2 | -45 | 11.4 | mV | VINN going negative until Gate Drive Turns ON | 4 |
| Regulated VINP/VSS to VINN Threshold | VSD(REG) | -10.8 | 12 | 30.8 | mV | 4 | |
| Gate Capacitance Discharge Time at Forward to Reverse Transition | tGATE(REV) | 34 | 50 | ns | CGATE = 0 (1) | 4 | |
| Gate Capacitance Discharge Time at Forward to Reverse Transition | tGATE(REV) | 90 | 230 | ns | CGATE = 47 nF (1) | 4 | |
| OFF Input High Threshold Voltage | VOFF(IH) | 1.28 | 1.5 | 1.65 | V | VINN = -400 mV, VOFF Rising until Gate is Low | 4 |
| OFF Pin Internal Pull-down | IOFF(IH) | 4.6 | 6 | µA | VOFF = 5.0V | 4 | |
| FET Test Threshold Voltage | VSD(TST) | -360 | -260 | -183 | mV | VOFF = 5.0V, VINN/VSS going negative from VINP until nFGD pin goes Hi-Z | 5 |
| nFGD Output Low Voltage | nFGDVOL | 285 | 450 | mV | VOFF = 5V, nFGD Output = On, InFGD = 1mA Sinking | 5 | |
| nFGD Output Leakage Current | nFGDIOL | 0.01 | 0.7 | µA | VOFF = 0V, nFGD Output = Off, VnFGD = 5.0V | 5 | |
| Input Bias Current | IINN | 3.1 | µA | VINN = 0.0V | 4 | ||
| Input Bias Current | IINN | 0.04 | µA | VINN = 90V | 4 | ||
| GATE Pin High Voltage | VGATE | 13 | V | VLINE = 48.0V | 4 | ||
| Reverse Threshold Hysteresis | ΔVSD(REV) | 50 | mV | VINN going positive from VSD(REV) Threshold until Gate Drive Turns OFF | 4 | ||
| Gate Capacitance Discharge Time at Forward to Reverse Transition | tGATE(REV) | 60 | ns | CGATE = 10 nF (1) | 4 | ||
| Gate Capacitance Discharge Time at OFF pin Low to High Transition | tGATE(OFF) | 120 | ns | CGATE = 47 nF (2), See Figure 7 | 4 | ||
| OFF Input Low Threshold Voltage | VOFF(IL) | 1.48 | V | VINN = -400 mV, VOFF Falling until Gate is High | 4 | ||
| OFF Threshold Voltage Hysteresis | ΔVOFF | 20 | mV | VOFF(IH) - VOFF(IL) | 4 | ||
| OFF Pin Current | IOFF(IL) | -0.03 | µA | VOFF = 0.0V | 4 | ||
| FET Test Threshold Voltage Hysteresis | ΔVSD(TST) | 6.5 | mV | VOFF = 5.0V, VINN going positive from VSD(TST) until nFGD pin goes Lo-Z | 5 |
CAD (KiCad official)
- Symbol:
LM5051MAE - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files:
lm5051mae-etched.step/lm5051mae-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5051mae.step/lm5051mae.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (27 pp, sha256
9107f8929e0b6cd1, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).