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LM5045SQX
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, WQFN-28-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM5045SQX
Texas Instruments · AC-DC Controllers And Regulators · WQFN-28-EP(5x5)
LM5045SQX from Texas Instruments, in a WQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SLOPE | output | Provides a slope-compensation ramp current source of 0 to 100 µA, and must be tied to AGND when slope compensation is not needed. |
| 2 | COMP | input | PWM input where the optocoupler current is pulled into an internal NPN mirror; zero current gives maximum duty cycle, 1 mA reduces duty cycle to zero, and COMP input current is limited to 10 mA absolute maximum. |
| 3 | REF | power_out | Provides a 5 V reference output limited to 15 mA, which must be locally decoupled with a ceramic capacitor. |
| 4 | RT | bidirectional | A resistor to AGND sets the oscillator frequency (25 kΩ gives 185-215 kHz per phase), and the pin also accepts AC-coupled sync pulses, with the resistor required in both free-running and synchronized operation. |
| 5 | AGND | power_in | Analog ground that must be connected directly to the power ground terminal and tied to PGND with a short direct connection under the IC. |
| 6 | RD1 | input | A resistor to AGND sets the synchronous rectifier front-edge delay T1 (20 kΩ gives 45-90 ns, 100 kΩ gives 232-388 ns) and limits the maximum duty cycle. |
| 7 | RD2 | input | A resistor to AGND sets the synchronous rectifier rear-edge delay T2 (20 kΩ gives 43-90 ns, 100 kΩ gives 227-384 ns). |
| 8 | RES | input | Restart timer pin where 30 µA charges the RES capacitor during current limit, and at 1.0 V the SS capacitor is discharged to disable outputs before the hiccup count of eight ramps between 2 V and 4 V completes. |
| 9 | SS | input | Soft-start input charged by an internal 20 µA source, where pulling it below 200 mV stops the PWM pulses on HO1/HO2/LO1/LO2 and turns off the synchronous rectifiers. |
| 10 | SSSR | input | Secondary-side soft-start pin that sets the synchronous rectifier ramp with a 20 µA charge source once SS exceeds 2 V and COMP current is below 800 µA. |
| 11 | SSOFF | input | Soft-stop disable pin, where connecting it to AGND gives soft stop on VIN UVLO and hiccup faults and connecting it to REF gives hard stop on any fault, with a VIH(min) of 2.8 V and a 200 kΩ pull-down. |
| 12 | HS2 | input | Switching node common to the high-side FET source, low-side FET drain and transformer primary for the second phase, with HS voltage to GND rated from -5 V to 105 V and negative excursions not allowed below VCC - 16 V. |
| 13 | HO2 | output | High-side gate driver output for the bridge upper MOSFET, capable of 1.5 A peak source and 2 A peak sink. |
| 14 | BST2 | power_in | Bootstrap pin that, with an external capacitor to HS2, supplies the HO2 high-side driver from VCC through an external diode, with a recommended value of 0.1 µF or greater. |
| 15 | SR2 | output | Synchronous rectifier gate control output capable of 100 mA peak source and 400 mA peak sink, with a 5 V signal amplitude limit. |
| 16 | LO2 | output | Low-side gate driver output capable of 1.5 A peak source and 2 A peak sink. |
| 17 | VCC | power_in | Startup regulator output initially regulated to 9.5 V (9.3-9.9 V) and reduced to 7.7 V after SSSR reaches 1 V, with recommended capacitor 0.47-10 µF and an external 10-14 V supply allowed to lower controller dissipation. |
| 18 | PGND | power_in | Power ground that must be connected directly to AGND under the IC with a short direct connection to avoid ground-bounce jitter. |
| 19 | LO1 | output | Low-side gate driver output capable of 1.5 A peak source and 2 A peak sink. |
| 20 | SR1 | output | Synchronous rectifier gate control output capable of 100 mA peak source and 400 mA peak sink, with a 5 V signal amplitude limit. |
| 21 | BST1 | power_in | Bootstrap pin that, with an external capacitor to HS1, supplies the HO1 high-side driver from VCC through an external diode, with a recommended value of 0.1 µF or greater. |
| 22 | HO1 | output | High-side gate driver output for the bridge upper MOSFET, capable of 1.5 A peak source and 2 A peak sink. |
| 23 | HS1 | input | Switching node common to the high-side FET source, low-side FET drain and transformer primary for the first phase, with HS voltage to GND rated from -5 V to 105 V and negative excursions not allowed below VCC - 16 V. |
| 24 | VIN | power_in | Input supply for the startup regulator with an operating range of 14 V to 100 V and transients up to 105 V, and it can be bypassed by an external regulator for inputs beyond that range. |
| 25 | UVLO | input | Line undervoltage input with 0.4 V standby enable and 1.25 V run threshold (1.18-1.32 V) plus 20 µA hysteresis sink, not to exceed 7 V. |
| 26 | OVP | input | Overvoltage/overtemperature shutdown input with a 1.25 V threshold (1.18-1.32 V), a 20 µA hysteresis current, and a maximum pin voltage of 7 V. |
| 27 | RAMP | input | PWM comparator ramp input that can carry the primary-current sense signal or a VIN-proportional feedforward ramp, reset to GND at the end of each cycle through a 5.5 Ω MOSFET. |
| 28 | CS | input | Current-sense input where the PWM pulse terminates when CS exceeds 750 mV (0.71-0.785 V), with a 40 ns internal blanking after switching. |
| 29 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | WQFN-28-EP(5x5) |
| Category | Power Management (PMIC) |
| Pins | 29 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND | -0.3 | 105 | V | 6 | |||
| HS to GND | -5 | 105 | V | 6 | |||
| BST1/BST2 to GND | -0.3 | 116 | V | 6 | |||
| BST1/BST2 to HS1/HS2 | -0.3 | 16 | V | 6 | |||
| HO1/HO2 to HS1/HS2 | -0.3 | V | 6 | ||||
| LO1/LO2/SR1/SR2 voltage | -0.3 | V | 6 | ||||
| VCC to GND | -0.3 | 16 | V | 6 | |||
| REF, SSOFF, RT, OVP, UVLO to GND | -0.3 | 7 | V | 6 | |||
| Ramp (SLOPE pin) | -0.3 | 7 | V | 6 | |||
| COMP | -0.3 | V | 6 | ||||
| COMP input current | 10 | mA | 6 | ||||
| All other inputs to GND | -0.3 | V | 6 | ||||
| Junction temperature | 150 | °C | 6 | ||||
| Storage temperature | Tstg | -55 | 150 | °C | 6 | ||
| VIN voltage | 14 | 100 | V | 6 | |||
| External voltage applied to VCC | 10 | 14 | V | 6 | |||
| Junction temperature (operating) | -40 | 125 | °C | 6 | |||
| SLOPE pin voltage | -0.3 | 2 | V | 6 | |||
| VCC1 VCC voltage | VCC1 | 9.3 | 9.6 | 9.9 | V | ICC= 10 mA (SSSR < 1 V) | 7 |
| VCC2 VCC voltage | VCC2 | 7.5 | 7.8 | 8.1 | V | ICC= 10 mA (SSSR > 1 V) | 7 |
| VCC current limit | ICC(Lim) | 60 | 80 | mA | VCC = 6V | 7 | |
| VCC undervoltage threshold, negative-going VCC | VCC(UV) | 5.9 | 6.3 | 6.7 | V | Negative-going VCC | 7 |
| VIN shutdown current | 300 | 520 | µA | VIN = 20V, VUVLO = 0V | 7 | ||
| VIN shutdown current | 350 | 550 | µA | VIN = 100V, VUVLO = 0V | 7 | ||
| REF voltage | VREF | 4.85 | 5 | 5.15 | V | IREF = 0mA | 7 |
| REF voltage regulation | 25 | 50 | mV | IREF = 0 to 10mA | 7 | ||
| REF current limit | IREF(Lim) | 15 | 20 | mA | VREF = 4.5V | 7 | |
| REF undervoltage threshold | VREFUV | 4.3 | 4.5 | 4.7 | V | Positive-going VREF | 7 |
| UVLO undervoltage threshold | VUVLO | 1.18 | 1.25 | 1.32 | V | 7 | |
| UVLO hysteresis current | IUVLO | 16 | 20 | 24 | µA | Sink current at UVLO pin when VUVLO < 1.25V | 7 |
| UVLO standby enable threshold | 0.32 | 0.4 | 0.48 | V | UVLO voltage rising | 7 | |
| OVP shutdown threshold | VOVP | 1.18 | 1.25 | 1.32 | V | OVP rising | 7 |
| OVP hysteresis pull-up current | 16 | 20 | 24 | µA | Source current at OVP when OVP > 1.25V | 7 | |
| SS charge current | ISS | 16 | 20 | 24 | µA | VSS = 0V | 7 |
| SSSR charge-enable SS threshold | 1.93 | 2 | 2.2 | V | ICOMP < 800µA | 7 | |
| SSSR charge current | ISSSR | 16 | 20 | 24 | µA | VSS > 2V, ICOMP < 800µA | 7 |
| SSSR discharge current 1 | ISSSR-DIS1 | 54 | 65 | 75 | µA | VUVLO < 1.25V | 7 |
| SSSR discharge current 2 | ISSSR-DIS2 | 109 | 125 | 147 | µA | VRES > 1V | 7 |
| Current limit threshold | VCS | 0.71 | 0.75 | 0.785 | V | 7 | |
| SSOFF input threshold | VIH(min) | 2.8 | V | 8 | |||
| Oscillator frequency FSW1 (LO1, half oscillator frequency) | FSW1 | 185 | 200 | 215 | kHz | RT = 25kΩ | 8 |
| Oscillator frequency FSW2 (LO1, half oscillator frequency) | FSW2 | 420 | 480 | 540 | kHz | RT = 10kΩ | 8 |
| RT sync threshold | 2.8 | 3 | 3.3 | V | 8 | ||
| SR trailing-edge delay (SR off to HO & LO both on) | T1 | 45 | 65 | 90 | ns | RD1 = 20kΩ | 9 |
| SR trailing-edge delay (SR off to HO & LO both on) | T1 | 232 | 300 | 388 | ns | RD1 = 100kΩ | 9 |
| SR leading-edge delay (HO or LO off to SR on) | T2 | 43 | 65 | 90 | ns | RD2 = 20kΩ | 9 |
| SR leading-edge delay (HO or LO off to SR on) | T2 | 227 | 300 | 384 | ns | RD2 = 100kΩ | 9 |
| COMP current to RAMP offset voltage | VPWM-OS | 680 | 800 | 940 | µA | VRAMP = 0V | 9 |
| SS to RAMP offset voltage | VSS-OS | 0.78 | 1 | 1.22 | V | VRAMP = 0V | 9 |
| BST undervoltage threshold | VBst uv | 3.8 | 4.7 | 5.6 | V | VBST, VHS rising | 9 |
| HO/LO low-level output voltage | VOL | 0.16 | 0.32 | V | IHO/LO = 100mA | 9 | |
| HO/LO high-level output voltage | VOH | 0.27 | 0.495 | V | IHO/LO = 100mA; VOHL = VCC, VLO; VOHH = VBST, VHO | 9 | |
| VIN operating current | IIN | 4 | mA | 7 | |||
| Slope compensation current ramp, peak RAMP current | ISLOPE | 100 | µA | 9 | |||
| HO/LO peak source current | IOHL | 1.5 | A | VHO/LO = 0V | 9 | ||
| HO/LO peak sink current | IOLL | 2 | A | VHO/LO = VCC | 9 | ||
| Thermal shutdown temperature | TSD | 160 | °C | 9 | |||
| Thermal shutdown hysteresis | 25 | °C | 9 | ||||
| Junction-to-ambient thermal resistance (RSG/WQFN package) | RθJA | 40 | °C/W | 6 | |||
| Junction-to-case (top) thermal resistance (RSG/WQFN package) | RθJC(top) | 4 | °C/W | 6 |
CAD (KiCad official)
- Symbol:
LM5045SQX - Footprint:
Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm - 3D model: WQFN-28-EP(5x5) (KiCad packages3D, STEP)
- 3D model files:
lm5045sqx-etched.step/lm5045sqx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5045sqx.step/lm5045sqx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (47 pp, sha256
47e7c49a68c6bd8e, retrieved 2026-10-21, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).