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Contents

README

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LM5039SQX

Texas Instruments · DC-DC Controllers · WQFN-24-EP(4x5)

LM5039SQX from Texas Instruments, in a WQFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 NC unconnected No electrical contact.
2 ACL input A capacitor connected between the ACL pin and GND operates as an integrator in the average current limit circuitry.
3 COMP input An external opto-coupler connected to the COMP pin sources current into an internal NPN current mirror to control PWM duty cycle.
4 RT input An external resistor connected between RT and AGND sets the internal oscillator frequency, normally regulated at 2V.
5 AGND power_in Analog Ground, connect directly to Power Ground.
6 CS input Current sense input driven by a signal representative of the primary current, with 600mV threshold for peak cycle-by-cycle limiting and 500mV threshold for average current limiting.
7 SS input An internal 110µA current source charges an external capacitor to set the soft-start rate.
8 DLY input An external resistor to ground sets the timing for the non-overlap time of HO to SR1 and LO to SR2.
9 RES input If the current limit is exceeded during any cycle, a 22µA current is sourced to the RES pin capacitor for hiccup mode restart control.
10 NC unconnected No electrical contact.
11 HB power_in Boost voltage for the HO driver; an external diode is required from VCC to HB and an external capacitor is required from HS to HB to power the gate driver.
12 HS power_in Switch node connection common to the transformer and both power switches, providing a return path for the HO gate driver.
13 HO output Output of the high side PWM gate driver, capable of sinking 2A peak current.
14 LO output Output of the low side PWM gate driver, capable of sinking 2A peak current.
15 PGND power_in Power Ground, connect directly to Analog Ground.
16 VCC power_out Output of the high voltage start-up regulator regulated to 7.6V.
17 SR2 output Synchronous rectifier driver output for control of the synchronous FET gate, capable of 0.5A peak current.
18 SR1 output Synchronous rectifier driver output for control of the synchronous FET gate, capable of 0.5A peak current.
19 REF power_out Output of 5V Reference with typical output current of 20mA, requiring local decoupling with a 0.1µF capacitor.
20 NC unconnected No electrical contact.
21 VIN power_in Input voltage source to the Start-up Regulator with operating input range of 13V to 100V with transient capability to 105V.
22 NC unconnected No electrical contact.
23 RAMP input Modulator ramp signal set by an external RC circuit from VIN, discharged at the conclusion of every cycle by an internal FET.
24 UVLO input Line Under-Voltage Lockout determined by an external voltage divider from the power source for shutdown and standby control.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24-EP(4x5)
Category Power Supply Chip
Pins 25

CAD (KiCad official)

  • Symbol: LM5039SQX
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: WQFN-24-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: lm5039sqx-etched.step / lm5039sqx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5039sqx.step / lm5039sqx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (35 pp, sha256 a662d4b1f77df0cf, retrieved 2026-09-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-4-6 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF