LM5036RJBR from Texas Instruments, in a WQFN-28-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	RES	input	RES is the hiccup mode restart timer input.
2	AGND	power_in	AGND is the analog ground reference pin.
3	COMP	input	COMP is the control current input to the half-bridge PWM comparator.
4	REF	output	REF is the 5-V reference regulator output.
5	RT/SYNC	input	RT/SYNC sets the oscillator frequency or accepts an external clock for synchronization.
6	RON	input	RON sets the auxiliary supply on-time control.
7	ON_OFF	input	ON_OFF is configurable for over-voltage protection (OVP) or latch mode, with an absolute maximum of 5 V to GND.
8	SS	input	SS is the soft-start input.
9	SSSR	input	SSSR is the synchronous rectifier soft-start input.
10	RD1	input	RD1 sets the synchronous rectifier trailing-edge delay and requires a resistor of at least 5 kΩ.
11	RD2	input	RD2 sets the synchronous rectifier leading-edge delay and requires a resistor of at least 5 kΩ.
12	FB_AUX	input	FB_AUX is the auxiliary supply output voltage feedback input, with an absolute maximum of 5 V to GND.
13	VIN	power_in	VIN is the input voltage pin, with a recommended range of 16 V to 100 V and an absolute maximum of 105 V to GND.
14	SW_AUX	input	SW_AUX is the auxiliary supply switch node.
15	BST_AUX	input	BST_AUX is the auxiliary supply high-side gate drive bootstrap pin.
16	PGND	power_in	PGND is the power ground pin.
17	VCC	power_in	VCC is the bias supply pin, with an external supply range of 8.5 V to 14 V.
18	LSG	output	LSG is the half-bridge low-side MOSFET gate driver output.
19	SR2	output	SR2 is the synchronous rectifier PWM control output.
20	SR1	output	SR1 is the synchronous rectifier PWM control output.
21	BST	input	BST is the half-bridge high-side gate drive bootstrap pin.
22	HSG	output	HSG is the half-bridge high-side MOSFET gate driver output.
23	SW	input	SW is the half-bridge switch node, with an absolute maximum of -5 V to 105 V to GND.
24	RAMP	input	RAMP is the ramp signal input to the half-bridge PWM comparator.
25	CS_POS	input	CS_POS is the positive input terminal of the current sense amplifier.
26	CS_NEG	input	CS_NEG is the negative input terminal of the current sense amplifier.
27	CS_SET	input	CS_SET sets the current limit.
28	UVLO	input	UVLO is the input undervoltage lockout pin.
29	Pad	power_in	The Pad is the exposed thermal pad, which is a ground connection.

Key specifications

Parameter	Value
Manufacturer	Texas Instruments
Package	WQFN-28-EP(5x5)
Category	Power Supply Chip
Pins	29

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Input voltage	VIN	16	100		V		6
External VCC supply voltage	VCC	8.5	14		V		6
RD1, RD2 resistor value	RDx	5			kΩ		6
Junction temperature	TJ	-40		125	°C		6
VIN to GND	VIN	-0.3		105	V		6
SW/SW_AUX to GND	SW/SW_AUX	-5		105	V		6
BST to SW, BST_AUX to SW_AUX	VBST-SW	-0.3		16	V		6
HSG to SW	VHSG-SW	-0.3		16	V		6
LSG to GND	VLSG	-0.3		16	V		6
SR1/SR2 to GND	VSR1/VSR2	-0.3		5	V		6
VCC to GND	VCC	-0.3		16	V		6
RT, UVLO, ON/OFF, RON, RAMP, RES, FB_AUX, CS_POS, CS_NEG, CS_SET to GND		-0.3		5	V		6
COMP to GND	COMP	-0.3			V		6
COMP input current	ICOMP			10	mA		6
Junction temperature	TJ			150	°C		6
Storage temperature	Tstg	-55		150	°C		6
VCC voltage	VCC	7.5	7.8	8.1	V	ICC = 10 mA	7
VCC current limit	ICC(Lim)	69	81	94	mA	VCC = 6 V, VIN = 20 V	7
VCC undervoltage threshold, positive going	VCC(UV)	7.4	7.7	8	V	Positive going Vcc	7
VCC undervoltage threshold, negative going	VCC(UV)	6.1	6.3	6.7	V	Negative going Vcc	7
VIN shutdown current		276	580	670	µA	VIN = 20 V, VUVLO = 0 V, RON = 100 kΩ	7
REF voltage	VREF	4.85	5	5.15	V	IREF = 0 mA	7
REF load regulation	VREF(REG)	24	37	57	mV	IREF = 0 to 25 mA	7
REF current limit	IREF(LIM)	28	39	47	mA	VREF = 4.5 V, VIN = 20 V	7
REF undervoltage threshold, positive going	VREF(UV)	4.3	4.5	4.7	V	Positive going VREF	7
UVLO threshold	VUVLO	1.205	1.25	1.305	V		7
UVLO hysteresis current	IUVLO	15	20	24	µA		7
Internal startup regulator enable threshold	VSD	0.34	0.38	0.41	V	SS = 0 V, FB_AUX = 2.5 V	7
ON_OFF threshold	VON_OFF	1.18	1.25	1.32	V		7
ON_OFF hysteresis current	IOVL	40	50	60	µA		7
SS charge current	ISS	17	20	24	µA	SS = 0 V	7
SS threshold to enable SSSR charge current	VSSSecEn	1.93	2.06	2.2	V	ICOMP < 800 µA	8
SSSR charge current	ISSSR	17	20	24	µA	SS > 2 V, ICOMP < 800 µA	8
Current limit setting voltage	VLIM	0.72	0.75	0.77	V		8
CS to gate driver output delay	tCSLSG	60	85	122	ns		8
CS leading-edge blanking	tCSBLK	33	53	76	ns		8
SS threshold to disable switching		865	1000	1198	mV		8
SS output low voltage		30	48	57	mV	Sinking 100 µA	8
SSSR threshold to reset SSSR cap clamp event counter	SR_CTR_TH	4.8	4.94	5.1	V		8
RES hiccup threshold	VRESTh1	0.9	1	1.04	V		8
SSSR hiccup blanking disable threshold	VHC_BLK_TH	5.26	5.5	5.66	V		8
Frequency (half oscillator frequency) at RT = 25 kΩ	fSW1	185	200	215	kHz	RT = 25 kΩ	8
Frequency (half oscillator frequency) at RT = 10 kΩ	fSW2	420	480	540	kHz	RT = 10 kΩ	8
BST undervoltage threshold	VBST(UV)	3.2	4.137	5.6	V	VBST - VSW rising	9
Low-state output voltage, primary gate drivers	VOL_PRI	0.1	0.3	0.41	V	IHSG/LSG = 100 mA	9
BST_AUX undervoltage threshold	VBST_AUX(UV)	3.5	5	6.5	V	VBST_AUX - VSW_AUX rising	9
AUX supply UVLO input voltage rising threshold	VAUX_UVLO	12.2	15	16	V		9
AUX supply UVLO input voltage falling threshold	VAUX_UVLO	7.9	11.2	12.7	V		9
OFF-state AUX voltage regulation level	VAUX-OFF	1.26	1.4	1.53	V		10
ON-state AUX voltage regulation level	VAUX-ON	0.95	1	1.04	V		10
AUX supply current limit threshold	IAUX(LIM)	150	200	250	mA		10
AUX supply thermal shutdown temperature	TSD_AUX		160		°C		10
Junction-to-ambient thermal resistance	RΘJA		29.9		°C/W		7
Peak source current, primary gate drivers	ISO_PRI		1		A	VHSG/LSG = 0V	9

CAD (KiCad official)

Symbol: LM5036RJBR
Footprint: Package_DFN_QFN:QFN-28-1EP_5x5mm_P0.5mm_EP3.35x3.35mm
3D model: WQFN-28-EP(5x5) (KiCad packages3D, STEP)
3D model files: lm5036rjbr-etched.step / lm5036rjbr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm5036rjbr.step / lm5036rjbr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Texas Instruments datasheet (68 pp, sha256 ad4696529814646c, retrieved 2026-11-05, tier: manufacturer)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

LM5036RJBR

Verified LM5036RJBR

Verification log 1 record

3D Model

Symbol & Footprint

Schematic Symbol

PCB Footprint

Datasheet

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