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LM5034MTCX
Public Made by Adomby adom
Texas Instruments AC-DC Controllers And Regulators, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LM5034MTCX
Texas Instruments · AC-DC Controllers And Regulators · TSSOP-20
LM5034MTCX from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OVLP | passive | An external resistor of 10 kΩ to 100 kΩ sets the overlap time of the active clamp outputs relative to the main outputs for both controllers, which creates the deadtime between each main switch and its active clamp switch. |
| 2 | VIN | power_in | Input supply to the startup regulator, with an operating input range of 13V to 100V and transient capability to 105V. |
| 3 | COMP1 | input | Voltage feedback input to the Controller 1 PWM comparator inverting input through a 3:1 divider, with an internal 5kΩ pull-up to +5.0V for the opto-coupler; the OUT1 duty cycle increases as COMP1 increases. |
| 4 | CS1 | input | Current sense input for Controller 1 current mode control and current limiting; OUT1 is terminated when CS1 exceeds 0.5V, and CS1 voltage must not exceed 1.25V. |
| 5 | SS1 | bidirectional | Soft-start pin for Controller 1 charged by an internal 50 µA current source to set the soft-start rate; forcing SS1 below 0.5V shuts off Controller 1. |
| 6 | UVLO | input | VIN under-voltage lockout pin set by an external resistor divider, with a 1.25V comparator reference and a switched 20 µA current source providing adjustable hysteresis. |
| 7 | VCC1 | power_out | Output of the 7.7V high voltage start-up regulator for Controller 1; the sum of currents drawn from VCC1 and VCC2 should not exceed 19 mA. |
| 8 | OUT1 | output | Main gate driver output to the Controller 1 primary-side switch, swinging between VCC1 and GND1 at a frequency equal to half the oscillator frequency. |
| 9 | AC1 | output | Active clamp gate driver output for the Controller 1 P-channel MOSFET, overlapping the leading and trailing edges of OUT1 by the interval set by the OVLP pin resistor. |
| 10 | GND1 | power_in | Ground connection for Controller 1, including the gate drivers, PWM controller, soft-start and support functions. |
| 11 | GND2 | power_in | Ground connection for Controller 2, including the gate drivers, PWM controller and soft-start. |
| 12 | AC2 | output | Active clamp gate driver output for the Controller 2 P-channel MOSFET, overlapping the leading and trailing edges of OUT2 by the interval set by the OVLP pin resistor. |
| 13 | OUT2 | output | Main gate driver output to the Controller 2 primary-side switch, swinging between VCC2 and GND2 at a frequency equal to half the oscillator frequency. |
| 14 | VCC2 | power_out | Output of the 7.7V high voltage start-up regulator for Controller 2; the sum of currents drawn from VCC1 and VCC2 should not exceed 19 mA. |
| 15 | RES | passive | An external capacitor sets the time delay before forced restart during sustained cycle-by-cycle current limiting; the hiccup mode comparator threshold is 2.55V. |
| 16 | SS2 | bidirectional | Soft-start pin for Controller 2 charged by an internal 50 µA current source to set the soft-start rate; forcing SS2 below 0.5V shuts off Controller 2. |
| 17 | CS2 | input | Current sense input for Controller 2 current mode control and current limiting; OUT2 is terminated when CS2 exceeds 0.5V, and CS2 voltage must not exceed 1.25V. |
| 18 | COMP2 | input | Voltage feedback input to the Controller 2 PWM comparator inverting input through a 3:1 divider, with an internal 5kΩ pull-up to +5.0V for the opto-coupler; the OUT2 duty cycle increases as COMP2 increases. |
| 19 | DCL | passive | An external resistor sets the maximum allowed duty cycle at OUT1 and OUT2. |
| 20 | RT/SYNC | input | An external resistor sets the oscillator frequency, and this pin also accepts AC-coupled synchronization pulses from an external source. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 20 |
CAD (KiCad official)
- Symbol:
LM5034MTCX - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
lm5034mtcx-etched.step/lm5034mtcx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm5034mtcx.step/lm5034mtcx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (38 pp, sha256
136a7b378bffc7ce, retrieved 2026-10-10, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM5034MTCX
**Texas Instruments** · AC-DC Controllers And Regulators · TSSOP-20
LM5034MTCX from Texas Instruments, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OVLP | passive | An external resistor of 10 kΩ to 100 kΩ sets the overlap time of the active clamp outputs relative to the main outputs for both controllers, which creates the deadtime between each main switch and its active clamp switch. |
| 2 | VIN | power_in | Input supply to the startup regulator, with an operating input range of 13V to 100V and transient capability to 105V. |
| 3 | COMP1 | input | Voltage feedback input to the Controller 1 PWM comparator inverting input through a 3:1 divider, with an internal 5kΩ pull-up to +5.0V for the opto-coupler; the OUT1 duty cycle increases as COMP1 increases. |
| 4 | CS1 | input | Current sense input for Controller 1 current mode control and current limiting; OUT1 is terminated when CS1 exceeds 0.5V, and CS1 voltage must not exceed 1.25V. |
| 5 | SS1 | bidirectional | Soft-start pin for Controller 1 charged by an internal 50 µA current source to set the soft-start rate; forcing SS1 below 0.5V shuts off Controller 1. |
| 6 | UVLO | input | VIN under-voltage lockout pin set by an external resistor divider, with a 1.25V comparator reference and a switched 20 µA current source providing adjustable hysteresis. |
| 7 | VCC1 | power_out | Output of the 7.7V high voltage start-up regulator for Controller 1; the sum of currents drawn from VCC1 and VCC2 should not exceed 19 mA. |
| 8 | OUT1 | output | Main gate driver output to the Controller 1 primary-side switch, swinging between VCC1 and GND1 at a frequency equal to half the oscillator frequency. |
| 9 | AC1 | output | Active clamp gate driver output for the Controller 1 P-channel MOSFET, overlapping the leading and trailing edges of OUT1 by the interval set by the OVLP pin resistor. |
| 10 | GND1 | power_in | Ground connection for Controller 1, including the gate drivers, PWM controller, soft-start and support functions. |
| 11 | GND2 | power_in | Ground connection for Controller 2, including the gate drivers, PWM controller and soft-start. |
| 12 | AC2 | output | Active clamp gate driver output for the Controller 2 P-channel MOSFET, overlapping the leading and trailing edges of OUT2 by the interval set by the OVLP pin resistor. |
| 13 | OUT2 | output | Main gate driver output to the Controller 2 primary-side switch, swinging between VCC2 and GND2 at a frequency equal to half the oscillator frequency. |
| 14 | VCC2 | power_out | Output of the 7.7V high voltage start-up regulator for Controller 2; the sum of currents drawn from VCC1 and VCC2 should not exceed 19 mA. |
| 15 | RES | passive | An external capacitor sets the time delay before forced restart during sustained cycle-by-cycle current limiting; the hiccup mode comparator threshold is 2.55V. |
| 16 | SS2 | bidirectional | Soft-start pin for Controller 2 charged by an internal 50 µA current source to set the soft-start rate; forcing SS2 below 0.5V shuts off Controller 2. |
| 17 | CS2 | input | Current sense input for Controller 2 current mode control and current limiting; OUT2 is terminated when CS2 exceeds 0.5V, and CS2 voltage must not exceed 1.25V. |
| 18 | COMP2 | input | Voltage feedback input to the Controller 2 PWM comparator inverting input through a 3:1 divider, with an internal 5kΩ pull-up to +5.0V for the opto-coupler; the OUT2 duty cycle increases as COMP2 increases. |
| 19 | DCL | passive | An external resistor sets the maximum allowed duty cycle at OUT1 and OUT2. |
| 20 | RT/SYNC | input | An external resistor sets the oscillator frequency, and this pin also accepts AC-coupled synchronization pulses from an external source. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-20 |
| Category | Power Management (PMIC) |
| Pins | 20 |
## CAD (KiCad official)
- Symbol: `LM5034MTCX`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `lm5034mtcx-etched.step` / `lm5034mtcx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm5034mtcx.step` / `lm5034mtcx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm5034) (38 pp, sha256 `136a7b378bffc7ce`, retrieved 2026-10-10, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm5034mtcx-datasheet.pdf)