component
LM43603PWPR
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Texas Instruments DC-DC Converters, TSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM43603PWPR
Texas Instruments · DC-DC Converters · TSSOP-16-EP
LM43603PWPR from Texas Instruments, in a TSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SW | output | Switching output of the regulator, internally connected to both power MOSFETs; connect to power inductor. |
| 2 | SW | output | Switching output of the regulator, internally connected to both power MOSFETs; connect to power inductor. |
| 3 | CBOOT | output | Bootstrap capacitor connection for high-side driver; connect 470-nF capacitor from CBOOT to SW. |
| 4 | VCC | power_out | Internal bias supply output for bypassing, 3.28V typical; connect bypass capacitor from this pin to AGND; do not connect external loading or short to ground during operation. |
| 5 | BIAS | power_in | Optional internal LDO supply input (3.3V to 28V); tie to VOUT when 3.3V ≤ VOUT ≤ 28V or to external 3.3V/5V rail; place 1-10µF bypass capacitor when used, tie to ground when not in use; do not float. |
| 6 | SYNC | input | Clock input to synchronize switching action to external clock from 200kHz to 2.2MHz; use proper high-speed termination; connect to ground if not used; do not float. |
| 7 | RT | input | Frequency programming input; connect resistor from this pin to AGND to program switching frequency (200kHz to 2.2MHz) or leave floating for 500kHz default. |
| 8 | PGOOD | tri_state | Open-drain power-good flag output; use 10kΩ to 100kΩ pullup resistor to logic rail no higher than 12V; provides 220µs deglitch delay. |
| 9 | FB | input | Feedback sense input pin; connect to midpoint of feedback divider to set VOUT; reference voltage 1.011V typical; do not short this pin to ground during operation. |
| 10 | AGND | power_in | Analog ground pin serving as ground reference for internal references and logic; connect to system ground. |
| 11 | SS/TRK | input | Soft-start control pin; leave floating for 4.1ms internal soft-start or connect capacitor to extend soft-start time; can connect external voltage ramp for output voltage tracking. |
| 12 | EN | input | Enable input to internal LDO and regulator; high enables operation and low disables; connect to VIN, resistor divider, or external voltage/logic source; do not float; 2.1V typical enable threshold. |
| 13 | VIN | power_in | Supply input pins to internal LDO and high-side power FET, 3.5V to 36V range; connect to power supply and bypass capacitors CIN; maintain short path to high-frequency bypass capacitor and PGND. |
| 14 | VIN | power_in | Supply input pins to internal LDO and high-side power FET, 3.5V to 36V range; connect to power supply and bypass capacitors CIN; maintain short path to high-frequency bypass capacitor and PGND. |
| 15 | PGND | power_in | Power ground pins connected internally to low-side power FET; connect to system ground, PAD, AGND, and ground pins of input/output capacitors; maintain short path to CIN. |
| 16 | PGND | power_in | Power ground pins connected internally to low-side power FET; connect to system ground, PAD, AGND, and ground pins of input/output capacitors; maintain short path to CIN. |
| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-16-EP |
| Category | Power Management (PMIC) |
| Pins | 17 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reference voltage at FB, TJ = 25 C | VFB | 1.004 | 1.011 | 1.018 | V | TJ = 25 C | 7 |
| Reference voltage at FB, TJ = -40 to 85 C | VFB | 0.994 | 1.011 | 1.026 | V | TJ = -40 C to 85 C | 7 |
| Reference voltage at FB, TJ = -40 to 125 C | VFB | 0.994 | 1.011 | 1.03 | V | TJ = -40 C to 125 C | 7 |
| Shutdown quiescent current | ISHDN | 1.2 | 3.1 | µA | VEN = 0 V | 6 | |
| Operating quiescent current (non-switching) from VIN | IQ-NONSW | 5 | 10 | µA | VEN = 3.3 V, VFB = 1.5 V, VBIAS = 3.4 V external | 6 | |
| Operating quiescent current (non-switching) from external VBIAS | IBIAS-NONSW | 85 | 130 | µA | VEN = 3.3 V, VFB = 1.5 V, VBIAS = 3.4 V external | 6 | |
| Enable input leakage current | ILKG-EN | 0.8 | 1.75 | µA | VEN = 3.3 V | 6 | |
| Precision enable level for switching and regulator output VOUT | VEN-VOUT-H | 2 | 2.2 | 2.42 | V | VENABLE high level | 6 |
| Internal LDO input change-over threshold to BIAS (rising) | VBIAS-ON | 2.94 | 3.15 | V | VBIAS rising threshold | 6 | |
| Input leakage current at FB pin | ILKG-FB | 0.2 | 65 | nA | FB = 1.011 V | 7 | |
| Peak inductor current limit | IHS-LIMIT | 4.4 | 5.5 | 6.4 | A | 7 | |
| Inductor current valley limit | ILS-LIMIT | 2.6 | 3 | 3.3 | A | 7 | |
| Soft-start charge current | ISSC | 1.25 | 2 | 2.75 | µA | 7 | |
| Power-good over voltage tripping threshold | VPGOOD-HIGH | 110 | 113 | % | % of FB voltage | 7 | |
| Power-good under voltage tripping threshold | VPGOOD-LOW | 77 | 88 | % | % of FB voltage | 7 | |
| PGOOD pin pull-down resistance when power bad | RPGOOD | 69 | 150 | Ω | VEN = 3.3 V | 7 | |
| PGOOD pin pull-down resistance when power bad | RPGOOD | 150 | 350 | Ω | VEN = 0 V | 7 | |
| Minimum input voltage for startup | VIN-MIN-ST | 3.8 | V | 6 | |||
| Minimum high side MOSFET ON time | tON-MIN | 125 | 165 | ns | 8 | ||
| Minimum high side MOSFET OFF time | tOFF-MIN | 200 | 250 | ns | 8 | ||
| Oscillator default frequency | FOSC-DEFAULT | 425 | 500 | 580 | kHz | RT pin open circuit | 8 |
| Minimum adjustable frequency | FADJ | 200 | kHz | With 1% resistors at RT pin | 8 | ||
| Maximum adjustable frequency | FADJ | 2200 | kHz | 8 | |||
| Sync clock high level threshold | VSYNC-HIGH | 2 | V | 8 | |||
| Sync clock low level threshold | VSYNC-LOW | 0.4 | V | 8 | |||
| Sync clock maximum duty cycle | DSYNC-MAX | 90 | % | 8 | |||
| Sync clock minimum duty cycle | DSYNC-MIN | 10 | % | 8 | |||
| Minimum sync clock ON and OFF time | TSYNC-MIN | 80 | ns | 8 | |||
| VIN to PGND | -0.3 | 42 | V | At maximum duty cycle of 0.01% | 5 | ||
| EN to PGND | -0.3 | V | Maximum is VIN+0.3 | 5 | |||
| FB, RT, SS/TRK to AGND | -0.3 | 3.6 | V | 5 | |||
| PGOOD to AGND | -0.3 | 15 | V | 5 | |||
| SYNC to AGND | -0.3 | 5.5 | V | 5 | |||
| BIAS to AGND | -0.3 | 30 | V | 30 V or VIN, whichever is lower | 5 | ||
| AGND to PGND | -0.3 | 0.3 | V | 5 | |||
| SW to PGND | -0.3 | V | Maximum is VIN+0.3 | 5 | |||
| SW to PGND less than 10 ns transients | -3.5 | 42 | V | less than 10 ns transients | 5 | ||
| CBOOT to SW | -0.3 | 5.5 | V | 5 | |||
| VCC to AGND | -0.3 | 3.6 | V | 5 | |||
| Storage temperature | Tstg | -65 | 150 | °C | 5 | ||
| VIN to PGND | 3.5 | 36 | V | 5 | |||
| EN | -0.3 | V | Maximum is VIN | 5 | |||
| FB | -0.3 | 1.1 | V | 5 | |||
| PGOOD | -0.3 | 12 | V | 5 | |||
| BIAS input not used | -0.3 | 0.3 | V | 5 | |||
| BIAS input used | 3.3 | 28 | V | 28 V or VIN, whichever is lower | 5 | ||
| AGND to PGND | -0.1 | 0.1 | V | 5 | |||
| Output voltage | VOUT | 1 | 28 | V | 5 | ||
| Output current | IOUT | 0 | 3 | A | 5 | ||
| Operating junction temperature range | TJ | -40 | 125 | °C | 5 | ||
| Junction-to-ambient thermal resistance (HTSSOP-16) | RθJA | 38.9 | °C/W | HTSSOP 16-pin, 4-layer JEDEC board per JESD 51-7; see Figure 98 for copper area | 6 | ||
| Junction-to-case (top) thermal resistance (HTSSOP-16) | RθJC(top) | 24.3 | °C/W | HTSSOP 16-pin, JESD 51-7 | 6 | ||
| Junction-to-board thermal resistance (HTSSOP-16) | RθJB | 19.9 | °C/W | HTSSOP 16-pin, JESD 51-7 | 6 | ||
| Junction-to-top characterization parameter (HTSSOP-16) | ψJT | 0.7 | °C/W | HTSSOP 16-pin, JESD 51-7 | 6 | ||
| Junction-to-board characterization parameter (HTSSOP-16) | ψJB | 19.7 | °C/W | HTSSOP 16-pin, JESD 51-7 | 6 | ||
| Junction-to-case (bottom) thermal resistance (HTSSOP-16) | RθJC(bot) | 1.7 | °C/W | HTSSOP 16-pin, JESD 51-7 | 6 |
CAD (KiCad official)
- Symbol:
LM43603PWPR - Footprint:
Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm - 3D model: TSSOP-16-EP (KiCad packages3D, STEP)
- 3D model files:
lm43603pwpr-etched.step/lm43603pwpr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm43603pwpr.step/lm43603pwpr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (59 pp, sha256
2642edca40e62388, retrieved 2026-09-23, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).