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LM43603AQPWPTQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+54@@ -0,0 +1,54 @@+# LM43603AQPWPTQ1++**Texas Instruments** · DC-DC Converters · HTSSOP-16-EP++LM43603AQPWPTQ1 from Texas Instruments, in a HTSSOP-16-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs; connect to the power inductor. |+| 2 | SW | power_out | Switching output of the regulator, internally connected to both power MOSFETs; connect to the power inductor. |+| 3 | CBOOT | passive | Bootstrap capacitor connection for the high-side driver; connect a high-quality 470-nF capacitor from CBOOT to SW. |+| 4 | VCC | power_out | Internal bias supply output for bypassing to AGND; do not connect external loading to this pin and never short it to ground during operation. |+| 5 | BIAS | power_in | Optional internal LDO supply input, recommended tied to VOUT for 3.3 V ≤ VOUT ≤ 28 V; BIAS pin voltage should never exceed VIN, and the pin must be tied to ground when unused and not left floating. |+| 6 | SYNC | input | Clock input to synchronize switching action to an external clock; use proper high-speed termination, connect to ground if not used, and do not float. |+| 7 | RT | passive | Resistor connection from this pin to AGND programs the switching frequency; leave floating for the 500 kHz default. |+| 8 | PGOOD | output | Open-drain power-good flag output; use a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V. |+| 9 | FB | input | Feedback sense input connected to the midpoint of the feedback divider to set VOUT; do not short this pin to ground during operation. |+| 10 | AGND | power_in | Analog ground pin serving as the ground reference for internal references and logic; connect to system ground. |+| 11 | SS/TRK | passive | Soft-start control pin: leave floating for internal soft-start slew rate, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking. |+| 12 | EN | input | Enable input to the internal LDO and regulator, high = ON and low = OFF; connect to VIN, a resistor divider, or an external voltage or logic source and do not float. |+| 13 | VIN | power_in | Supply input to the internal LDO and high-side power FET; bypass with CIN and keep the path from VIN to CIN and PGND as short as possible. |+| 14 | VIN | power_in | Supply input to the internal LDO and high-side power FET; bypass with CIN and keep the path from VIN to CIN and PGND as short as possible. |+| 15 | PGND | power_in | Power ground pin connected internally to the low-side power FET; connect to system ground, PAD, AGND and the CIN and COUT grounds. |+| 16 | PGND | power_in | Power ground pin connected internally to the low-side power FET; connect to system ground, PAD, AGND and the CIN and COUT grounds. |+| 17 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | Texas Instruments |+| Package | HTSSOP-16-EP |+| Category | Power Supply Chip |+| Pins | 17 |++## CAD (KiCad official)++- Symbol: `LM43603AQPWPTQ1`+- Footprint: `Package_SO:TSSOP-16-1EP_4.4x5mm_P0.65mm`+- 3D model: HTSSOP-16-EP (KiCad packages3D, STEP)+- 3D model files: `lm43603aqpwptq1-etched.step` / `lm43603aqpwptq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm43603aqpwptq1.step` / `lm43603aqpwptq1.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm43603-q1) (50 pp, sha256 `a594b61b24d8e622`, retrieved 2026-10-08, tier: lcsc)+- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lm43603aqpwptq1-datasheet.pdf)
page.jsonadded+256@@ -0,0 +1,256 @@+{+ "slug": "lm43603aqpwptq1",+ "version": "0.1.0",+ "type": "component",+ "description": "Texas Instruments DC-DC Converters, HTSSOP-16-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power supply chip",+ "lm43603aqpwptq1",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lm43603aqpwptq1.kicad_sym",+ "lm43603aqpwptq1.kicad_mod",+ "lm43603aqpwptq1.glb",+ "lm43603aqpwptq1.step",+ "lm43603aqpwptq1.lbr",+ "docs/hero.png",+ "docs/lm43603aqpwptq1-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html",+ "lm43603aqpwptq1-hero.glb",+ "lm43603aqpwptq1-hero.overlay.json"+ ],+ "component": {+ "mpn": "LM43603AQPWPTQ1",+ "manufacturer": "Texas Instruments",+ "package": "HTSSOP-16-EP",+ "pin_count": 17,+ "category": "Power Supply Chip",+ "subcategory": "DC-DC Converters",+ "datasheet": "https://www.ti.com/cn/lit/gpn/lm43603-q1",+ "parts": {+ "symbol": "lm43603aqpwptq1.kicad_sym",+ "footprint": "lm43603aqpwptq1.kicad_mod",+ "model_3d": "lm43603aqpwptq1-hero.glb",+ "model_3d_plain": "lm43603aqpwptq1.glb",+ "model_3d_step": "lm43603aqpwptq1-etched.step",+ "model_3d_step_plain": "lm43603aqpwptq1.step",+ "lbr": "lm43603aqpwptq1.lbr"+ },+ "distributor_links": {+ "lcsc": "C2070846",+ "digikey": "296-46642-2-ND",+ "mouser": "595-LM43603AQPWPTQ1"+ },+ "distributor_check": {+ "checked_at": "2026-10-08T15:27:46Z",+ "source": "Component Ocean /api/assign-pns",+ "digikey": {+ "pn": "296-46642-2-ND",+ "status": "found",+ "lifecycle": "Active"+ },+ "mouser": {+ "pn": "595-LM43603AQPWPTQ1",+ "status": "found"+ }+ },+ "pins": [+ {+ "number": "1",+ "name": "SW",+ "type": "power_out",+ "description": "Switching output of the regulator, internally connected to both power MOSFETs; connect to the power inductor."+ },+ {+ "number": "2",+ "name": "SW",+ "type": "power_out",+ "description": "Switching output of the regulator, internally connected to both power MOSFETs; connect to the power inductor."+ },+ {+ "number": "3",+ "name": "CBOOT",+ "type": "passive",+ "description": "Bootstrap capacitor connection for the high-side driver; connect a high-quality 470-nF capacitor from CBOOT to SW."+ },+ {+ "number": "4",+ "name": "VCC",+ "type": "power_out",+ "description": "Internal bias supply output for bypassing to AGND; do not connect external loading to this pin and never short it to ground during operation."+ },+ {+ "number": "5",+ "name": "BIAS",+ "type": "power_in",+ "description": "Optional internal LDO supply input, recommended tied to VOUT for 3.3 V ≤ VOUT ≤ 28 V; BIAS pin voltage should never exceed VIN, and the pin must be tied to ground when unused and not left floating."+ },+ {+ "number": "6",+ "name": "SYNC",+ "type": "input",+ "description": "Clock input to synchronize switching action to an external clock; use proper high-speed termination, connect to ground if not used, and do not float."+ },+ {+ "number": "7",+ "name": "RT",+ "type": "passive",+ "description": "Resistor connection from this pin to AGND programs the switching frequency; leave floating for the 500 kHz default."+ },+ {+ "number": "8",+ "name": "PGOOD",+ "type": "output",+ "description": "Open-drain power-good flag output; use a 10-kΩ to 100-kΩ pullup to a logic rail or DC voltage no higher than 12 V."+ },+ {+ "number": "9",+ "name": "FB",+ "type": "input",+ "description": "Feedback sense input connected to the midpoint of the feedback divider to set VOUT; do not short this pin to ground during operation."+ },+ {+ "number": "10",+ "name": "AGND",+ "type": "power_in",+ "description": "Analog ground pin serving as the ground reference for internal references and logic; connect to system ground."+ },+ {+ "number": "11",+ "name": "SS/TRK",+ "type": "passive",+ "description": "Soft-start control pin: leave floating for internal soft-start slew rate, connect a capacitor to extend soft-start time, or connect an external voltage ramp for tracking."+ },+ {+ "number": "12",+ "name": "EN",+ "type": "input",+ "description": "Enable input to the internal LDO and regulator, high = ON and low = OFF; connect to VIN, a resistor divider, or an external voltage or logic source and do not float."+ },+ {+ "number": "13",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input to the internal LDO and high-side power FET; bypass with CIN and keep the path from VIN to CIN and PGND as short as possible."+ },+ {+ "number": "14",+ "name": "VIN",+ "type": "power_in",+ "description": "Supply input to the internal LDO and high-side power FET; bypass with CIN and keep the path from VIN to CIN and PGND as short as possible."+ },+ {+ "number": "15",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground pin connected internally to the low-side power FET; connect to system ground, PAD, AGND and the CIN and COUT grounds."+ },+ {+ "number": "16",+ "name": "PGND",+ "type": "power_in",+ "description": "Power ground pin connected internally to the low-side power FET; connect to system ground, PAD, AGND and the CIN and COUT grounds."+ },+ {+ "number": "17",+ "name": "EP",+ "type": "passive",+ "description": "Exposed pad (from the footprint; not named in the datasheet pin table)."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.3",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.3",+ "primary_model": "claude-haiku-5-5",+ "primary_mode": "text",+ "consensus_model": "claude-sonnet-5-5",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The datasheet is the LM43603-Q1 datasheet (SNVSA82/ZHCSDR3C). The orderable LM43603AQPWPTQ1 (A varia; The exposed thermal pad is listed in the pin table as 'PAD' with no pin number. It is reported as nu; The KiCad types for CBOOT, RT and SS/TRK are judgment calls, since the datasheet gives only the 'P' ",+ "exposed pad 17 added from the footprint",+ "dropped thermal pad ['EP'] absent from footprint"+ ],+ "pages_sent": 8,+ "cost_usd": 0.0712,+ "at": "2026-10-08T15:27:23"+ },+ "datasheet": {+ "url": "https://www.ti.com/cn/lit/gpn/lm43603-q1",+ "pages": 50,+ "sha256": "a594b61b24d8e622",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 17,+ "described": 17,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ },+ "models_3d": [+ {+ "file": "lm43603aqpwptq1.step",+ "role": "plain",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "7982746831c0bd23f4690608869ad67776faae5c762fb0376666126a3998921b",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ },+ {+ "file": "lm43603aqpwptq1-etched.step",+ "role": "eda",+ "up": "Z",+ "units": "mm",+ "origin": "footprint origin = pad-pattern centre",+ "seat": "z = 0",+ "extents_mm": [+ 6.4,+ 5,+ 1.1+ ],+ "zmin_mm": 0,+ "centre_offset_mm": 0,+ "footprint_binding": "identity",+ "sha256": "c9181b1b5fe46c646379bb59ceb3eac96f5e6355cddda4206501c1cfe42feafc",+ "checked": "2026-10-08",+ "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"+ }+ ]+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}