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LM34966QPWPRQ1

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Texas Instruments DC-DC Controllers, HTSSOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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LM34966QPWPRQ1

Texas Instruments · DC-DC Controllers · HTSSOP-14

LM34966QPWPRQ1 from Texas Instruments, in a HTSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BIAS power_in Supply voltage input to the VCC regulator; connect a bypass capacitor from this pin to PGND (absolute maximum 45 V).
2 NC unconnected No electrical contact.
3 VCC power_out Output of the internal VCC regulator and supply input of the MOSFET driver; connect a ceramic bypass capacitor from this pin to PGND.
4 GATE output N-channel MOSFET gate drive output; connect directly to the MOSFET gate through a short, low inductance path.
5 PGND power_in Power ground pin; connect directly to the ground of the sense resistor through a low inductance wide and short path.
6 AGND power_in Analog ground pin; connect directly to the analog ground plane through a wide and short path.
7 CS input Current sense input; connect to the positive side of the current sense resistor through a short path.
8 COMP output Output of the internal transconductance error amplifier; connect the loop compensation components between this pin and the ground plane.
9 VDD power_in Input of the internal logic; connect directly to VCC.
10 FB input Inverting input of the error amplifier; connect a voltage divider from the output to set output voltage, with the low-side resistor to AGND.
11 SS input Soft-start time programming pin; an external capacitor to AGND and an internal current source set the reference ramp rate.
12 RT input Switching frequency setting pin; frequency is programmed by a single resistor between RT and AGND.
13 PGOOD output Open-drain power-good output that goes low if FB is below the undervoltage threshold; use a pullup resistor or leave floating if unused.
14 EN/UVLO/SYNC input Programs undervoltage lockout start-up and shutdown levels via a divider and accepts a negative pulse for external clock synchronization; must not be left floating, connect to BIAS if not used.
15 EP power_in Exposed pad; must be connected to AGND and the large ground copper plane to decrease thermal resistance.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-14
Category Power Supply Chip
Pins 15

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
BIAS shutdown current ISHUTDOWN(BIAS) 2.6 6 μA VBIAS = 12 V, VUVLO = 0 V 5
BIAS operating current IOPERATING(BIAS) 490 1200 μA VBIAS = 12 V, VUVLO = 2.0 V, VFB = VREF, RT = 220 kΩ 5
VCC regulation VVCC-REG 6.5 6.85 7 V VBIAS = 8 V, No load 5
VCC regulation (loaded) VVCC-REG 6.5 V VBIAS = 8 V, IVCC = 35 mA 5
VCC UVLO threshold VVCC-UVLO(RISING) 2.75 2.85 2.95 V VCC rising 5
VCC UVLO hysteresis 0.063 V VCC falling 5
VCC sourcing current limit IVCC-CL 20 110 mA VBIAS = 10 V, VVCC = 0 V 5
Enable threshold rising VEN(RISING) 0.4 0.52 0.7 V EN rising 6
Enable threshold falling VEN(FALLING) 0.33 0.49 0.63 V EN falling 6
Enable hysteresis VEN(HYS) 0.03 V EN falling 6
UVLO / SYNC threshold rising VUVLO(RISING) 1.425 1.5 1.575 V UVLO rising 6
UVLO / SYNC threshold falling VUVLO(FALLING) 1.37 1.45 1.52 V UVLO falling 6
UVLO / SYNC threshold hysteresis VUVLO(HYS) 0.05 V UVLO falling 6
UVLO hysteresis current IUVLO 4 5 6 μA VUVLO = 1.6 V 6
Soft-start current ISS 9 10 11 μA 6
SS pull-down switch rDS(on) rDS(on) 55 Ω 6
Switching frequency fsw 85 100 115 kHz RT = 220 kΩ, VBIAS = 4 V 6
Maximum duty cycle limit DMAX 90 93 96 % RT = 220 kΩ, VBIAS = 4 V 6
Peak slope compensation current ISLOPE 22.5 30 37.5 μA RT = 220 kΩ 6
Current limit threshold (CS-PGND) VCLTH 93 100 107 mV 6
Hiccup enable cycles 64 Cycles 6
Hiccup timer reset cycles 8 Cycles 6
FB reference VREF 0.99 1 1.01 V 6
Transconductance Gm 2 mA/V 6
COMP sourcing current 180 μA VCOMP = 1.2V 6
COMP clamp voltage rising 2.5 2.8 V COMP rising (VUVLO = 2.0 V) 6
COMP clamp voltage falling 1 1.15 V COMP falling 6
Over-voltage threshold rising VOVTH 107 110 113 % FB rising (in reference to VREF) 6
Over-voltage threshold falling VOVTH 105 % FB falling (in reference to VREF) 6
PGOOD pull-down switch rDS(on) rDS(on) 90 Ω 1 mA sinking 6
Under-voltage threshold falling VUVTH 87 90 93 % FB falling (in reference to VREF) 6
Under-voltage threshold rising VUVTH 95 % FB rising (in reference to VREF) 6
MOSFET driver high-state voltage drop 0.25 V 100 mA sinking 6
MOSFET driver low-state voltage drop 0.15 V 100 mA sourcing 6
Thermal shutdown threshold TTSD 175 °C Temperature rising 6
Thermal shutdown hysteresis 15 °C 6
Bias input VBIAS 2.97 40 V 5
VCC voltage VVCC 2.97 16 V 5
VDD input VVDD 2.1 16 V 5
UVLO input VUVLO 0 40 V 5
FB input VFB 0 4 V 5
Typical switching frequency fSW 100 500 kHz 5
Synchronization pulse frequency fSYNC 100 500 kHz 5
Operating junction temperature TJ -40 150 °C 5
BIAS to AGND -0.3 45 V 4
UVLO to AGND -0.3 45 V VBIAS+0.3 4
SS to AGND -0.3 3.8 V 4
RT to AGND -0.3 3.8 V 4
FB to AGND -0.3 4 V 4
CS to AGND (DC) -0.3 0.3 V 4
CS to AGND (50ns transient) -1 V 50ns transient 4
PGND to AGND -0.3 0.3 V 4
VDD to AGND -0.3 18 V 4
VCC to AGND -0.3 18 V 18 V or VBIAS + 0.3 V whichever is lower 4
GATE to AGND (50ns transient) -1 V 50ns transient 4
PGOOD to AGND -0.3 18 V 4
Junction temperature TJ -40 150 °C 4
Storage temperature Tstg -55 150 °C 4
Junction-to-ambient thermal resistance RθJA 44.1 °C/W PWP (HTSSOP) 14 pins 5
Junction-to-case (top) thermal resistance RθJC(top) 49.1 °C/W PWP (HTSSOP) 14 pins 5

CAD (KiCad official)

  • Symbol: LM34966QPWPRQ1
  • Footprint: Package_SO:TSSOP-14-1EP_4.4x5mm_P0.65mm
  • 3D model: HTSSOP-14 (KiCad packages3D, STEP)
  • 3D model files: lm34966qpwprq1-etched.step / lm34966qpwprq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm34966qpwprq1.step / lm34966qpwprq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (45 pp, sha256 50b45891edffe0df, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF