# LM34936QPWPRQ1

**Texas Instruments** · DC-DC Converters · TSSOP-28-EP

LM34936QPWPRQ1 from Texas Instruments, in a TSSOP-28-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EN/UVLO | input | Enable pin: below 0.4 V the device is in low current shutdown, above 1.22 V the PWM function is enabled provided VCC exceeds the VCC UV threshold. |
| 2 | VIN | power_in | Input supply pin to the IC; connect to a supply voltage between 4.2 V and 30 V. |
| 3 | VISNS | input | VIN sense input; connect to the power stage input rail. |
| 4 | MODE | input | Selects hiccup mode: 1.38 V to 2.22 V is CCM with hiccup enabled (RMODE to AGND = 93.1 kΩ), 2.6 V to VCC is CCM with hiccup disabled (200 kΩ or connect to VCC). |
| 5 | DITH | input | A capacitor to AGND sets dithering that modulates the oscillator frequency by 10% of the nominal RT frequency; grounding the pin disables dithering, and it is ignored in external Sync mode. |
| 6 | RT/SYNC | input | Switching frequency programming pin: a resistor to AGND sets the switching frequency, and the pin can also synchronize the PWM controller to an external clock. |
| 7 | SLOPE | passive | A capacitor to AGND provides the slope compensation ramp for stable current mode operation in both Buck and Boost mode. |
| 8 | SS | passive | Soft-start programming pin; a capacitor between SS and AGND sets the soft-start time. |
| 9 | COMP | output | Output of the error amplifier; an external RC network between COMP and AGND compensates the feedback loop. |
| 10 | AGND | power_in | Analog ground of the IC. |
| 11 | FB | input | Feedback pin for output voltage regulation; connect a resistor divider from the converter output to FB. |
| 12 | VOSNS | input | VOUT sense input; connect to the power stage output rail. |
| 13 | ISNS(-) | input | Input or output current sense amplifier input; when the voltage across ISNS(+) and ISNS(-) reaches 50 mV a slow constant current loop regulates it to 50 mV, and shorting ISNS(+) and ISNS(-) disables the feature. |
| 14 | ISNS(+) | input | Input or output current sense amplifier input; when the voltage across ISNS(+) and ISNS(-) reaches 50 mV a slow constant current loop regulates it to 50 mV, and shorting ISNS(+) and ISNS(-) disables the feature. |
| 15 | CSG | input | Negative or ground input to the PWM current sense amplifier; connect directly to the low-side (ground) of the current sense resistor. |
| 16 | CS | input | Positive input to the PWM current sense amplifier. |
| 17 | PGOOD | output | Power-Good open-drain output that is pulled low when FB is outside a -9%/+10% regulation window around the 0.8-V VREF. |
| 18 | SW2 | passive | Boost side switching node. |
| 19 | HDRV2 | output | Output of the high-side gate driver; connect directly to the gate of the high-side MOSFET. |
| 20 | BOOT2 | passive | Bootstrap pin; an external capacitor is required between BOOT2 and SW2 to bias the high-side MOSFET gate driver. |
| 21 | LDRV2 | output | Output of the low-side gate driver; connect directly to the gate of the low-side MOSFET. |
| 22 | PGND | power_in | Power ground of the IC; the high current ground connection to the low-side gate drivers. |
| 23 | VCC | power_out | Output of the VCC bias regulator; connect a capacitor to ground. |
| 24 | BIAS | power_in | Optional input to the VCC bias regulator; for VBIAS > 8 V the VCC regulator draws power from BIAS, which can reduce power loss at high VIN. |
| 25 | LDRV1 | output | Output of the low-side gate driver; connect directly to the gate of the low-side MOSFET. |
| 26 | BOOT1 | passive | Bootstrap pin; an external capacitor is required between BOOT1 and SW1 to bias the high-side MOSFET gate driver. |
| 27 | HDRV1 | output | Output of the high-side gate driver; connect directly to the gate of the high-side MOSFET. |
| 28 | SW1 | passive | Buck side switching node. |
| 29 | PowerPAD | power_in | Exposed PowerPAD should be soldered to analog ground, with thermal vias to a PCB ground plane if possible for improved power dissipation. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | TSSOP-28-EP |
| Category | Power Management (PMIC) |
| Pins | 29 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN shutdown current | IQ |  | 2.6 | 10 | µA | VEN/UVLO = 0 V | 6 |
| VIN operating current |  |  | 2 | 4 | mA | VEN/UVLO = 2 V, VFB = 0.9 V | 6 |
| VCC regulation voltage | VVCC(VIN) | 6.95 | 7.35 | 7.88 | V | VBIAS = 0 V, VCC open | 6 |
| VCC undervoltage lockout | VUV(VCC) | 3.11 | 3.27 | 3.43 | V | VCC increasing | 6 |
| VCC regulator output impedance | ROUT(VCC) |  | 8 | 16 | Ω | IVCC = 30 mA, VIN = 4 V | 6 |
| BIAS switchover voltage | VBIAS(SW) | 7.25 | 8 | 8.75 | V | VIN = 24 V | 6 |
| Standby threshold | VEN(STBY) | 0.55 | 0.82 | 0.97 | V | EN/UVLO rising | 6 |
| Standby source current | IEN(STBY) | 1 | 2 | 3 | µA | VEN/UVLO = 1.1 V | 6 |
| Operating threshold | VEN(OP) | 1.17 | 1.22 | 1.29 | V | EN/UVLO rising | 6 |
| Operating hysteresis current | ΔIHYS(OP) | 2.15 | 3.15 | 4.25 | µA | VEN/UVLO = 1.5 V | 6 |
| Soft-start pullup current | ISS | 3.75 | 5 | 6.35 | µA | VSS = 0 V | 6 |
| Feedback reference voltage | VREF | 0.788 | 0.8 | 0.812 | V | FB = COMP | 6 |
| Switching frequency 1 | fSW(1) | 175 | 200 | 225 | kHz | RT = 40 kΩ | 6 |
| Switching frequency 2 | fSW(2) | 350 | 390 | 430 | kHz | RT = 20 kΩ | 6 |
| Buck current limit threshold (valley) | VCS(BUCK) | 66 | 80 | 94 | mV | VIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V | 7 |
| Boost current limit threshold (peak) | VCS(BOOST) | 100 | 120 | 140 | mV | VIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V | 7 |
| Average current loop regulation target | VSNS | 43 | 50 | 57 | mV | VISNS(-) = 24 V, sweep ISNS(+), VSS = 0.8 V | 7 |
| Buck adaptive slope current | ISLOPE | 24 | 30 | 35 | µA | VIN = VVISNS = 24 V, VVOSNS = 12 V, VSLOPE = 0 V | 7 |
| Boost adaptive slope current | ISLOPE | 13 | 17 | 21 | µA | VIN = VVISNS = 12 V, VVOSNS = 18 V, VSLOPE = 0 V | 7 |
| Source current out of MODE pin | IMODE | 17 | 20 | 23 | µA |  | 7 |
| CCM with hiccup threshold | VCCM_HIC | 1.18 | 1.28 | 1.38 | V |  | 7 |
| CCM no hiccup threshold | VCCM | 2.22 | 2.4 | 2.6 | V |  | 7 |
| PGOOD sink current | ISINK(PGD) | 2 | 4.2 | 6.5 | mA | VPGOOD = 0.4 V | 7 |
| VIN input bias voltage | VIN | 4.2 |  | 30 | V |  | 5 |
| Input power stage voltage with external bias | VISNS | 2.5 |  | 30 | V | BIAS ≥ 5 V or VIN ≥ 4.5 V | 5 |
| Bias supply voltage range (when VCC in regulation) | BIAS | 8 |  | 30 | V |  | 5 |
| Output voltage range | VOSNS | 0.8 |  | 30 | V |  | 5 |
| Enable voltage range | EN/UVLO | 0 |  | 30 | V |  | 5 |
| Average current sense common mode range | ISNS(+), ISNS(-) | 0 |  | 30 | V |  | 5 |
| Operating temperature range (junction) | TJ | -40 |  | 150 | °C |  | 5 |
| Operating frequency range | Fsw | 100 |  | 600 | kHz |  | 5 |
| VIN, EN/UVLO, VISNS, VOSNS, ISNS(+), ISNS(–) |  | -0.3 |  | 42 | V |  | 5 |
| BIAS |  | -0.3 |  | 40 | V |  | 5 |
| FB, SS, DITH, RT/SYNC, SLOPE, COMP |  | -0.3 |  | 3.6 | V |  | 5 |
| SW1, SW2 |  | -1 |  | 42 | V |  | 5 |
| SW1, SW2 transient |  | -5 |  | 47 | V | 20 ns transient | 5 |
| VCC, MODE, PGOOD |  | -0.3 |  | 8.5 | V |  | 5 |
| LDRV1, LDRV2 |  | -0.3 |  | 8.5 | V |  | 5 |
| BOOT1, HDRV1 with respect to SW1 |  | -0.3 |  | 8.5 | V | with respect to SW1 | 5 |
| BOOT2, HDRV2 with respect to SW2 |  | -0.3 |  | 8.5 | V | with respect to SW2 | 5 |
| BOOT1, BOOT2 |  | -0.3 |  | 55 | V |  | 5 |
| ISNS(+) with respect to ISNS(–) |  | -0.3 |  | 0.3 | V |  | 5 |
| CS, CSG |  | -0.3 |  | 0.3 | V |  | 5 |
| Operating junction temperature |  | -40 |  | 150 | °C |  | 5 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 5 |
| Junction-to-ambient thermal resistance | RθJA |  | 32.6 |  | °C/W |  | 6 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 21.4 |  | °C/W |  | 6 |
| Junction-to-board thermal resistance | RθJB |  | 8.2 |  | °C/W |  | 6 |
| Junction-to-top characterization parameter | ψJT |  | 0.3 |  | °C/W |  | 6 |
| Junction-to-board characterization parameter | ψJB |  | 8.3 |  | °C/W |  | 6 |
| Junction-to-case (bottom) thermal resistance | RθJC(bot) |  | 1 |  | °C/W |  | 6 |

## CAD (KiCad official)

- Symbol: `LM34936QPWPRQ1`
- Footprint: `Package_SO:TSSOP-28-1EP_4.4x9.7mm_P0.65mm_EP2.85x6.7mm`
- 3D model: TSSOP-28-EP (KiCad packages3D, STEP)
- 3D model files: `lm34936qpwprq1-etched.step` / `lm34936qpwprq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm34936qpwprq1.step` / `lm34936qpwprq1.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm34936-q1) (41 pp, sha256 `4ca152db4a27eff3`, retrieved 2026-10-12, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lm34936qpwprq1-datasheet.pdf)