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LM317LDR2G-HXY

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HXY MOSFET Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM317LDR2G-HXY

HXY MOSFET · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOP-8

LM317LDR2G-HXY from HXY MOSFET, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADJ passive Adjustment terminal: VOUT = 1.25V(1+R2/R1)+IADJ·R2, and IADJ is controlled to less than 100uA so its error is negligible in most applications.
2 VIN power_in Regulator input; the input-output voltage differential must not exceed 40V (absolute maximum), and CIN is required when the regulator is far from the supply filter.
3 VIN power_in Regulator input; the input-output voltage differential must not exceed 40V (absolute maximum), and CIN is required when the regulator is far from the supply filter.
4 VOUT power_out Regulator output, adjustable from 1.2V to 37V, with output current exceeding 100mA.
5 N.C. unconnected Not connected; listed as N.C. in the pin table.
6 VIN power_in Regulator input; the input-output voltage differential must not exceed 40V (absolute maximum), and CIN is required when the regulator is far from the supply filter.
7 VIN power_in Regulator input; the input-output voltage differential must not exceed 40V (absolute maximum), and CIN is required when the regulator is far from the supply filter.
8 N.C. unconnected Not connected; listed as N.C. in the pin table.

Key specifications

Parameter Value
Manufacturer HXY MOSFET
Package SOP-8
Category Power Management (PMIC)
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Line Regulation ΔVo 0.01 0.04 %/V TA=-40 ∼125℃, 3V≤VI-VO≤40V 2
Line Regulation ΔVo 0.02 0.07 %/V 3V≤VI-VO≤40V 2
Load Regulation ΔVo 10 25 mV TA=25℃, 10㎃≤Io≤IMAX, VO≤5V 2
Load Regulation ΔVo 0.1 0.5 %/V TA=25℃, 10㎃≤Io≤IMAX, VO≥5V 2
Load Regulation ΔVo 20 80 mV 10㎃≤Io≤IMAX, VO≤5V 2
Load Regulation ΔVo 0.3 1.7 %/V 10㎃≤Io≤IMAX, VO≥5V 2
Adjustable Pin Current IADJ 46 100 ㎂ 2
Adjustable Pin Current Change ΔIADJ 0.2 5 ㎂ 3V≤VI-VO≤40V, 10㎃≤IO≤IMAX, P≤PMAX 2
Reference Voltage VREF 1.2 1.25 1.3 V 3V≤VIN-VOUT≤40V, 10㎃≤Io≤IMAX, PD≤PMAX 2
Minimum Load Current to Maintain Regulation L(MIN) 3.5 10 mA VI-Vo=40V 2
Maximum Output Current IO(MAX) 100 200 mA VI-Vo≤5V, PD≤PMAX 2
Maximum Output Current IO(MAX) 0.156 0.4 mA VI-VO≤40V, PD≤PMAX, TA=25℃ 2
RMS Noise, % of VOUT eN 0.003 0.01 %/VO TA=25℃, 10Hz≤f≤10KHz 2
Ripple Rejection RR 66 75 dB VO=10V, f=120Hz, CADJ=10㎌ 2
Long-Term Stability ST 0.3 1 % TA=25℃, for end point measurements, 1000HR 2
Input-output Voltage Differential VI-VO 40 V 2
Lead Temperature (Soldering, 10 sec) TSOL 230 ℃ Soldering, 10 sec 2
Operating Junction Temperature Range TJOPR -40 125 ℃ 2
Storage Temperature Range TSTG -65 125 ℃ 2

CAD (KiCad official)

  • Symbol: LM317LDR2G-HXY
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: lm317ldr2g-hxy-etched.step / lm317ldr2g-hxy-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm317ldr2g-hxy.step / lm317ldr2g-hxy.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: HXY MOSFET datasheet (4 pp, sha256 fe6be4eafc3a8204, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF