# LM2904VDR2G

**onsemi** · Operational Amplifier · SOIC-8

LM2904VDR2G from onsemi, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUTPUT A | output | Output of amplifier A; the output voltage swing includes the negative supply rail, with a typical low limit of 5.0 mV and a short-circuit duration that is continuous. |
| 2 | INPUTS A - | input | Inverting input of amplifier A; the input common mode voltage must not go negative by more than 0.3 V below ground/VEE. |
| 3 | INPUTS A + | input | Non-inverting input of amplifier A; the common mode range extends to the negative supply and the upper end is VCC - 1.7 V. |
| 4 | VEE/GND | power_in | Negative supply rail (ground in single-supply operation); the common mode range extends to this pin. |
| 5 | INPUTS B + | input | Non-inverting input of amplifier B; the common mode range extends to the negative supply and the upper end is VCC - 1.7 V. |
| 6 | INPUTS B - | input | Inverting input of amplifier B; the input common mode voltage must not go negative by more than 0.3 V below ground/VEE. |
| 7 | OUTPUT B | output | Output of amplifier B; the output voltage range includes the negative supply rail and the output is short-circuit protected. |
| 8 | VCC | power_in | Positive supply; single-supply operation from 3.0 V to 32 V, with a maximum of 32 Vdc. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | onsemi |
| Package | SOIC-8 |
| Category | Amplifiers/Comparators |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input Offset Voltage (TA = 25°C) | VIO |  |  | 7 | mV | VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V, VO  1.4 V, RS = 0; TA = 25°C | 5 |
| Input Offset Voltage (TA = Thigh) | VIO |  |  | 13 | mV | VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V, VO  1.4 V, RS = 0; TA = Thigh (Note 7) | 5 |
| Input Offset Voltage (TA = Tlow) | VIO |  |  | 10 | mV | VCC = 5.0 V to 30 V, VIC = 0 V to VCC −1.7 V, VO  1.4 V, RS = 0; TA = Tlow (Note 7) | 5 |
| Input Offset Current | IIO |  | 5 | 50 | nA |  | 5 |
| Input Offset Current (TA = Thigh to Tlow) | IIO |  | 45 | 200 | nA | TA = Thigh to Tlow (Note 7) | 5 |
| Input Bias Current | IIB |  | -45 | -250 | nA |  | 5 |
| Input Bias Current (TA = Thigh to Tlow) | IIB |  | -50 | -500 | nA | TA = Thigh to Tlow (Note 7) | 5 |
| Input Common Mode Voltage Range | VICR | 0 |  | 28.3 | V | VCC = 30 V | 5 |
| Input Common Mode Voltage Range (TA = Thigh to Tlow) | VICR | 0 |  | 28 | V | VCC = 30 V, TA = Thigh to Tlow | 5 |
| Large Signal Open Loop Voltage Gain | AVOL | 25 | 100 |  | V/mV | RL = 2.0 k, VCC = 15 V, For Large VO Swing | 5 |
| Large Signal Open Loop Voltage Gain (TA = Thigh to Tlow) | AVOL | 15 |  |  | V/mV | TA = Thigh to Tlow (Note 7) | 5 |
| Common Mode Rejection | CMR | 50 | 70 |  | dB | RS ≤ 10 k | 5 |
| Power Supply Rejection | PSR | 50 | 100 |  | dB |  | 5 |
| Output Voltage−High Limit (VCC = 5.0 V) | VOH | 3.3 | 3.5 |  | V | VCC = 5.0 V, RL = 2.0 k, TA = 25°C | 5 |
| Output Voltage−High Limit (VCC = 30 V, RL = 2.0 k) | VOH | 26 |  |  | V | VCC = 30 V, RL = 2.0 k | 5 |
| Output Voltage−High Limit (VCC = 30 V, RL = 10 k) | VOH | 27 | 28 |  | V | VCC = 30 V, RL = 10 k | 5 |
| Output Voltage−Low Limit | VOL |  | 5 | 20 | mV | VCC = 5.0 V, RL = 10 k, TA = Thigh to Tlow (Note 7) | 5 |
| Output Source Current | IO+ | 20 | 40 |  | mA | VID = +1.0 V, VCC = 15 V | 5 |
| Output Sink Current | IO− | 10 | 20 |  | mA | VID = −1.0 V, VCC = 15 V | 5 |
| Output Short Circuit to Ground | ISC |  | 40 | 60 | mA |  | 5 |
| Power Supply Current (Total Device) | ICC |  | 1.5 | 3 | mA | VCC = 30 V, VO = 0 V, RL = ∞; TA = Thigh to Tlow (Note 7) | 5 |
| Power Supply Current (Total Device) | ICC |  | 0.7 | 1.2 | mA | VCC = 5 V, VO = 0 V, RL = ∞; TA = Thigh to Tlow (Note 7) | 5 |
| Power Supply Voltage, Single Supply | VCC |  |  | 32 | Vdc | Single Supply | 3 |
| Power Supply Voltage, Split Supplies | VCC, VEE | -16 |  | 16 | Vdc | Split Supplies (Note 1) | 3 |
| Input Differential Voltage Range | VIDR | -32 |  | 32 | Vdc | Note 1 | 3 |
| Input Common Mode Voltage Range | VICR | -0.3 |  | 32 | Vdc |  | 3 |
| Junction Temperature | TJ |  |  | 150 | °C |  | 3 |
| Storage Temperature Range | Tstg | -65 |  | 150 | °C |  | 3 |
| Operating Ambient Temperature Range | TA | -40 |  | 125 | °C | LM2904V, NCV2904 (Note 3) | 3 |
| ESD Protection, Human Body Model |  |  |  | 2000 | V | HBM, All Other Devices | 3 |
| ESD Protection, Machine Model |  |  |  | 200 | V | MM, All Other Devices | 3 |
| Thermal Resistance, Junction-to-Air | RJA |  | 212 |  | °C/W | Case 751 (SOIC-8), Note 2 | 3 |

## CAD (KiCad official)

- Symbol: `LM2904VDR2G`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `lm2904vdr2g-etched.step` / `lm2904vdr2g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm2904vdr2g.step` / `lm2904vdr2g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [onsemi datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893431658139648) (16 pp, sha256 `c8db41089b6c5181`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lm2904vdr2g-datasheet.pdf)