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LM26420Q0XMH

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Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM26420Q0XMH

Texas Instruments · DC-DC Converters · HTSSOP-20-EP

LM26420Q0XMH from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VINC power_in Supply for the control circuit and the high- and low-side gate drivers; it must not be lower than VIND1,2 - VTH, and an RC filter to AGND (RF typically 1 to 10 ohm, CF 0.22 to 1 uF in X7R/X5R) is recommended.
2 EN1 input Enable input for buck converter 1 with logic-high enable (threshold about 1.04 V with 150 mV hysteresis); do not leave it floating or drive it above VIN + 0.3 V.
3 VIND1 power_in Input power supply for buck converter 1, operating over 3 V to 5.5 V with an absolute maximum of 7 V; place at least one 10 uF X7R/X5R ceramic capacitor next to each VIND pin.
4 VIND1 power_in Input power supply for buck converter 1, operating over 3 V to 5.5 V with an absolute maximum of 7 V; place at least one 10 uF X7R/X5R ceramic capacitor next to each VIND pin.
5 SW1 power_out Output switch node of buck converter 1 that connects to the inductor; absolute maximum voltage is -0.5 V to 7 V.
6 PGND1 power_in Power ground for buck converter 1, which should be kept close to the input capacitor ground and tied to the ground plane with at least two vias.
7 PGND1 power_in Power ground for buck converter 1, which should be kept close to the input capacitor ground and tied to the ground plane with at least two vias.
8 FB1 input Feedback input for buck converter 1 from the external resistor divider that sets VOUT (VREF 0.8 V, absolute maximum -0.5 V to 3 V); keep this high-impedance trace short.
9 PG1 output Open-drain power-good output for buck converter 1 that requires an external pull-up resistor (10 kohm to 100 kohm, 50 kohm recommended) and is high when FB is within the power-good window.
10 DAP passive Die attach pad connection that should be tied to system ground for low thermal impedance, but this pin cannot be used as the main GND connection.
11 DAP passive Die attach pad connection that should be tied to system ground for low thermal impedance, but this pin cannot be used as the main GND connection.
12 PG2 output Open-drain power-good output for buck converter 2 that requires an external pull-up resistor (10 kohm to 100 kohm) and is high when FB2 is within the power-good window.
13 FB2 input Feedback input for buck converter 2 from the external resistor divider that sets VOUT (VREF 0.8 V, absolute maximum -0.5 V to 3 V); keep this high-impedance trace short.
14 PGND2 power_in Power ground for buck converter 2, which should be kept close to the input capacitor ground and tied to the ground plane with at least two vias.
15 PGND2 power_in Power ground for buck converter 2, which should be kept close to the input capacitor ground and tied to the ground plane with at least two vias.
16 SW2 power_out Output switch node of buck converter 2 that connects to the inductor; absolute maximum voltage is -0.5 V to 7 V.
17 VIND2 power_in Input power supply for buck converter 2, operating over 3 V to 5.5 V with an absolute maximum of 7 V; place at least one 10 uF X7R/X5R ceramic capacitor next to each VIND pin.
18 VIND2 power_in Input power supply for buck converter 2, operating over 3 V to 5.5 V with an absolute maximum of 7 V; place at least one 10 uF X7R/X5R ceramic capacitor next to each VIND pin.
19 EN2 input Enable input for buck converter 2 with logic-high enable (threshold about 1.04 V with 150 mV hysteresis); do not leave it floating or drive it above VIN + 0.3 V.
20 AGND power_in Signal ground; the bottom resistor of the feedback network should be placed as close as possible to this pin.
21 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package HTSSOP-20-EP
Category Power Management (PMIC)
Pins 21

CAD (KiCad official)

  • Symbol: LM26420Q0XMH
  • Footprint: Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm
  • 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: lm26420q0xmh-etched.step / lm26420q0xmh-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm26420q0xmh.step / lm26420q0xmh.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (47 pp, sha256 b25d3310c3924b09, retrieved 2026-10-08, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF