component
LM26003MHX
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
main
LM26003MHX
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
LM26003MHX from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power supply input for the high side FET. |
| 2 | VIN | power_in | Power supply input for the high side FET. |
| 3 | VIN | power_in | Power supply input for the high side FET. |
| 4 | AVIN | power_in | Power supply input for the IC supply. |
| 5 | PGOOD | output | Open-drain power good output that goes high when the output voltage is greater than 92% of nominal. |
| 6 | EN | input | Analog level enable input; when pulled below 0.8 V the device enters shutdown mode. |
| 7 | SS | input | Soft-start pin; connect a capacitor from this pin to GND to set the soft-start time. |
| 8 | COMP | input | Compensation pin; connect a resistor capacitor pair to compensate the control loop. |
| 9 | FB | input | Feedback pin; connect a resistor divider between VOUT and GND to set the output voltage. |
| 10 | AGND | power_in | Analog GND serves as the IC reference. |
| 11 | PGND | power_in | Power GND is the GND for the switching stage of the regulator. |
| 12 | FREQ | output | Frequency adjust pin; connect a resistor from this pin to GND to set the operating frequency. |
| 13 | FPWM | input | Logic level input; for normal operation connect to GND, and when pulled high sleep mode operation is disabled. |
| 14 | SYNC | input | Frequency synchronization pin; connect to an external clock for synchronized operation and pull low for non-synchronized operation. |
| 15 | VBIAS | input | Connect to an external 3-V or greater supply to bypass the internal regulator; tie to GND if not used. |
| 16 | VDD | power_in | Output of the internal regulator; bypass with a minimum 1.0-µF capacitor. |
| 17 | BOOT | input | Bootstrap capacitor pin; connect a 0.1-µF minimum ceramic capacitor from this pin to SW. |
| 18 | SW | output | Switch pin; the source of the internal N-channel switch. |
| 19 | SW | output | Switch pin; the source of the internal N-channel switch. |
| 20 | SW | output | Switch pin; the source of the internal N-channel switch. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN voltage absolute maximum | VIN | -0.3 | 40 | V | 4 | ||
| SW voltage absolute maximum | SW | -1 | 40 | V | 4 | ||
| VDD voltage absolute maximum | VDD | -0.3 | 7 | V | 4 | ||
| VBIAS voltage absolute maximum | VBIAS | -0.3 | 10 | V | 4 | ||
| FB voltage absolute maximum | FB | -0.3 | 7 | V | 4 | ||
| PGOOD voltage absolute maximum | PGOOD | -0.3 | 7 | V | 4 | ||
| FREQ voltage absolute maximum | FREQ | -0.3 | 7 | V | 4 | ||
| SYNC voltage absolute maximum | SYNC | -0.3 | 7 | V | 4 | ||
| EN voltage absolute maximum | EN | -0.3 | 40 | V | 4 | ||
| FPWM voltage absolute maximum | FPWM | -0.3 | 7 | V | 4 | ||
| Power dissipation absolute maximum | 3.1 | W | 4 | ||||
| Storage temperature | Tstg | -65 | 150 | °C | 4 | ||
| Vapor phase lead temperature | 215 | °C | Vapor Phase (70s) | 4 | |||
| Infrared lead temperature | 220 | °C | Infrared (15s) | 4 | |||
| Operating junction temperature | TJ | -40 | 125 | °C | 4 | ||
| Supply voltage | VIN | 3 | 38 | V | 4 | ||
| Shutdown current | ISD | 10.8 | µA | EN = 0 V | 5 | ||
| Shutdown current over temperature | ISD | 20 | µA | EN = 0 V, -40°C ≤ TJ ≤ 125°C | 5 | ||
| Quiescent current sleep mode, VBIAS=5V | IqSleep_VB | 40 | µA | Sleep mode, VBIAS = 5 V | 5 | ||
| Quiescent current sleep mode, VBIAS=5V over temperature | IqSleep_VB | 70 | µA | Sleep mode, VBIAS = 5 V, -40°C ≤ TJ ≤ 125°C | 5 | ||
| Quiescent current sleep mode, VBIAS=GND | IqSleep_VDD | 76 | µA | Sleep mode, VBIAS = GND | 5 | ||
| Quiescent current sleep mode, VBIAS=GND over temperature | IqSleep_VDD | 125 | µA | Sleep mode, VBIAS = GND, -40°C ≤ TJ ≤ 125°C | 5 | ||
| Quiescent current PWM mode, VBIAS=5V | IqPWM_VB | 0.16 | 0.23 | mA | PWM mode, VBIAS = 5 V, FPWM = 2 V | 5 | |
| Quiescent current PWM mode, VBIAS=GND | IqPWM_VDD | 0.65 | 0.85 | mA | PWM mode, VBIAS = GND, FPWM = 2 V | 5 | |
| Bias current sleep mode | IBIAS_Sleep | 33 | µA | Sleep mode, VBIAS = 5 V | 5 | ||
| Bias current sleep mode over temperature | IBIAS_Sleep | 60 | µA | Sleep mode, VBIAS = 5 V, -40°C ≤ TJ ≤ 125°C | 5 | ||
| Bias current PWM mode | IBIAS_PWM | 0.5 | 0.7 | mA | PWM mode, VBIAS = 5 V | 5 | |
| Feedback voltage over temperature | VFB | 1.217 | 1.255 | V | 5 V < Vin < 38 V, -40°C ≤ TJ ≤ 125°C | 5 | |
| FB bias current | IFB | -200 | 200 | nA | VFB = 1.20 V | 5 | |
| VDD pin output voltage at 5 mA | VDD | 5.99 | V | 7 V < Vin < 35 V, IVDD = 0 mA to 5 mA | 5 | ||
| VDD pin output voltage over temperature | VDD | 5.5 | 6.5 | V | 7 V < Vin < 35 V, IVDD = 0 mA to 5 mA, -40°C ≤ TJ ≤ 125°C | 5 | |
| Soft-start source current over temperature | ISS_Source | 1.5 | 4.6 | µA | -40°C ≤ TJ ≤ 125°C | 5 | |
| VBIAS on voltage | Vbias_th | 2.64 | 2.9 | 3.07 | V | Specified at IBIAS = 92.5% of full value | 5 |
| Peak current limit over temperature | ILIMPK | 3.15 | 6.05 | A | -40°C ≤ TJ ≤ 125°C | 6 | |
| PGOOD threshold over temperature | VTH_PGOOD | 89 | 95 | % | Measured at FB, PGOOD rising, -40°C ≤ TJ ≤ 125°C | 6 | |
| PGOOD hysteresis | 2 | 6 | 8 | % | 6 | ||
| UVLO threshold falling over temperature | VUVLO | 2.7 | 3.3 | V | Vin falling, shutdown, VDD = 2.70 V, -40°C ≤ TJ ≤ 125°C | 6 | |
| UVLO threshold rising over temperature | VUVLO | 3.7 | 4.3 | V | Vin rising, soft-start, VDD = VIN, -40°C ≤ TJ ≤ 125°C | 6 | |
| Enable threshold voltage over temperature | VthEN | 0.8 | 1.4 | V | Enable rising, -40°C ≤ TJ ≤ 125°C | 6 | |
| FPWM threshold over temperature | VTH_FPWM | 0.8 | 1.6 | V | -40°C ≤ TJ ≤ 125°C | 6 | |
| Error amp transconductance over temperature | gm | 400 | 1000 | µmho | -40°C ≤ TJ ≤ 125°C | 6 | |
| COMP pin voltage range | VCOMP | 0.64 | 1.27 | V | 6 | ||
| Switch on resistance over temperature | RDS(ON) | 0.04 | 0.2 | Ω | Isw = 2A, -40°C ≤ TJ ≤ 125°C | 7 | |
| Switch off state leakage over temperature | Isw_off | 5 | µA | Vin = 38 V, VSW = 0 V, -40°C ≤ TJ ≤ 125°C | 7 | ||
| Switching frequency tolerance | fsw | -10 | 10 | % | RFREQ = 62k, 124k, 240k, -40°C ≤ TJ ≤ 125°C | 7 | |
| Switching frequency range | fSW | 150 | 500 | kHz | -40°C ≤ TJ ≤ 125°C | 7 | |
| Upper frequency synchronization range | FSYNC_UP | 30 | % | As compared to nominal fSW, -40°C ≤ TJ ≤ 125°C | 7 | ||
| Lower frequency synchronization range | FSYNC_DN | -20 | % | As compared to nominal fSW, -40°C ≤ TJ ≤ 125°C | 7 | ||
| Sync pin threshold rising over temperature | VSYNC | 1.6 | V | SYNC rising, -40°C ≤ TJ ≤ 125°C | 7 | ||
| Sync pin threshold falling over temperature | VSYNC | 0.8 | V | SYNC falling, -40°C ≤ TJ ≤ 125°C | 7 | ||
| Break-before-make BOOT leakage over temperature | IBOOT | 5 | µA | BOOT = 6 V, SW = GND, -40°C ≤ TJ ≤ 125°C | 7 | ||
| Thermal shutdown threshold | TSD | 160 | °C | 6 | |||
| Thermal resistance junction-to-ambient | θJA | 32 | °C/W | Power dissipation = 1W, 0 lfpm air flow | 6 | ||
| Junction-to-ambient thermal resistance (PWP 20 pins) | RθJA | 25.4 | °C/W | 5 | |||
| Junction-to-case (top) thermal resistance (PWP 20 pins) | RθJC(top) | 19.6 | °C/W | 5 | |||
| Junction-to-board thermal resistance (PWP 20 pins) | RθJB | 16.5 | °C/W | 5 | |||
| Junction-to-case (bottom) thermal resistance (PWP 20 pins) | RθJC(bot) | 0.8 | °C/W | 5 | |||
| Quiescent current in shutdown | ISD | 10.8 | µA | EN = 0 V | 5 | ||
| Feedback voltage | VFB | 1.236 | V | 5 V < Vin < 38 V | 5 | ||
| Output voltage line regulation | ΔVOUT/ΔVIN | 0.00025 | %/V | 5 V < Vin < 38 V | 5 | ||
| Output voltage load regulation | ΔVOUT/ΔIOUT | 0.08 | %/A | 0.8 V < VCOMP < 1.15 V | 5 | ||
| Soft-start source current | ISS_Source | 2.5 | µA | 5 | |||
| Peak current limit | ILIMPK | 4.7 | A | 6 | |||
| Short circuit frequency foldback threshold | VFB_SC | 0.87 | V | Measured at FB falling | 6 | ||
| Min frequency in foldback | F_min_sc | 45 | kHz | VFB < 0.3 V | 6 | ||
| PGOOD threshold | VTH_PGOOD | 92 | % | Measured at FB, PGOOD rising | 6 | ||
| PGOOD on resistance | RDS_PGOOD | 150 | Ω | PGOOD sink current = 500 µA | 6 | ||
| PGOOD leakage current | IPGOOD_HI | 1.25 | nA | PGOOD = 5 V | 6 | ||
| UVLO threshold falling | VUVLO | 2.96 | V | Vin falling, shutdown, VDD = 2.96 V | 6 | ||
| UVLO threshold rising | VUVLO | 3.99 | V | Vin rising, soft-start, VDD = VIN | 6 | ||
| Enable threshold voltage | VthEN | 1.18 | V | Enable rising | 6 | ||
| Enable hysteresis | 180 | mV | 6 | ||||
| EN source current | IEN_Source | 4.85 | µA | EN = 0 V | 6 | ||
| FPWM threshold | VTH_FPWM | 1.24 | V | 6 | |||
| Error amp transconductance | gm | 675 | µmho | 6 | |||
| COMP source current | ICOMP | 57 | µA | VCOMP = 0.9 V | 6 | ||
| COMP sink current | ICOMP | 57 | µA | VCOMP = 0.9 V | 6 | ||
| Switch on resistance | RDS(ON) | 0.095 | Ω | Isw = 2A | 7 | ||
| Switch off state leakage current | Isw_off | 0.002 | µA | Vin = 38 V, VSW = 0 V | 7 | ||
| FREQ voltage | VFREQ | 1 | V | 7 | |||
| Sync pin threshold rising | VSYNC | 1.23 | V | SYNC rising | 7 | ||
| Sync pin threshold falling | VSYNC | 1.1 | V | SYNC falling | 7 | ||
| Sync pin hysteresis | 135 | mV | 7 | ||||
| SYNC leakage current | ISYNC | 2 | nA | 7 | |||
| Minimum off-time | TOFFMIN | 300 | ns | 7 | |||
| Minimum on-time | TONMIN | 190 | ns | 7 | |||
| Sleep mode threshold hysteresis | THSLEEP_HYS | 101.3 | % | VFB rising, % of THWAKE | 7 | ||
| Wake up threshold | THWAKE | 1.236 | V | Measured at falling FB, COMP = 0.6 | 7 | ||
| BOOT pin leakage current | IBOOT | 0.001 | µA | BOOT = 6 V, SW = GND | 7 |
CAD (KiCad official)
- Symbol:
LM26003MHX - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files:
lm26003mhx-etched.step/lm26003mhx-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm26003mhx.step/lm26003mhx.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (35 pp, sha256
e141f2bc565d916a, retrieved 2026-11-05, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM26003MHX
**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP
LM26003MHX from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power supply input for the high side FET. |
| 2 | VIN | power_in | Power supply input for the high side FET. |
| 3 | VIN | power_in | Power supply input for the high side FET. |
| 4 | AVIN | power_in | Power supply input for the IC supply. |
| 5 | PGOOD | output | Open-drain power good output that goes high when the output voltage is greater than 92% of nominal. |
| 6 | EN | input | Analog level enable input; when pulled below 0.8 V the device enters shutdown mode. |
| 7 | SS | input | Soft-start pin; connect a capacitor from this pin to GND to set the soft-start time. |
| 8 | COMP | input | Compensation pin; connect a resistor capacitor pair to compensate the control loop. |
| 9 | FB | input | Feedback pin; connect a resistor divider between VOUT and GND to set the output voltage. |
| 10 | AGND | power_in | Analog GND serves as the IC reference. |
| 11 | PGND | power_in | Power GND is the GND for the switching stage of the regulator. |
| 12 | FREQ | output | Frequency adjust pin; connect a resistor from this pin to GND to set the operating frequency. |
| 13 | FPWM | input | Logic level input; for normal operation connect to GND, and when pulled high sleep mode operation is disabled. |
| 14 | SYNC | input | Frequency synchronization pin; connect to an external clock for synchronized operation and pull low for non-synchronized operation. |
| 15 | VBIAS | input | Connect to an external 3-V or greater supply to bypass the internal regulator; tie to GND if not used. |
| 16 | VDD | power_in | Output of the internal regulator; bypass with a minimum 1.0-µF capacitor. |
| 17 | BOOT | input | Bootstrap capacitor pin; connect a 0.1-µF minimum ceramic capacitor from this pin to SW. |
| 18 | SW | output | Switch pin; the source of the internal N-channel switch. |
| 19 | SW | output | Switch pin; the source of the internal N-channel switch. |
| 20 | SW | output | Switch pin; the source of the internal N-channel switch. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management (PMIC) |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN voltage absolute maximum | VIN | -0.3 | | 40 | V | | 4 |
| SW voltage absolute maximum | SW | -1 | | 40 | V | | 4 |
| VDD voltage absolute maximum | VDD | -0.3 | | 7 | V | | 4 |
| VBIAS voltage absolute maximum | VBIAS | -0.3 | | 10 | V | | 4 |
| FB voltage absolute maximum | FB | -0.3 | | 7 | V | | 4 |
| PGOOD voltage absolute maximum | PGOOD | -0.3 | | 7 | V | | 4 |
| FREQ voltage absolute maximum | FREQ | -0.3 | | 7 | V | | 4 |
| SYNC voltage absolute maximum | SYNC | -0.3 | | 7 | V | | 4 |
| EN voltage absolute maximum | EN | -0.3 | | 40 | V | | 4 |
| FPWM voltage absolute maximum | FPWM | -0.3 | | 7 | V | | 4 |
| Power dissipation absolute maximum | | | | 3.1 | W | | 4 |
| Storage temperature | Tstg | -65 | | 150 | °C | | 4 |
| Vapor phase lead temperature | | | | 215 | °C | Vapor Phase (70s) | 4 |
| Infrared lead temperature | | | | 220 | °C | Infrared (15s) | 4 |
| Operating junction temperature | TJ | -40 | | 125 | °C | | 4 |
| Supply voltage | VIN | 3 | | 38 | V | | 4 |
| Shutdown current | ISD | | | 10.8 | µA | EN = 0 V | 5 |
| Shutdown current over temperature | ISD | | | 20 | µA | EN = 0 V, -40°C ≤ TJ ≤ 125°C | 5 |
| Quiescent current sleep mode, VBIAS=5V | IqSleep_VB | | | 40 | µA | Sleep mode, VBIAS = 5 V | 5 |
| Quiescent current sleep mode, VBIAS=5V over temperature | IqSleep_VB | | | 70 | µA | Sleep mode, VBIAS = 5 V, -40°C ≤ TJ ≤ 125°C | 5 |
| Quiescent current sleep mode, VBIAS=GND | IqSleep_VDD | | | 76 | µA | Sleep mode, VBIAS = GND | 5 |
| Quiescent current sleep mode, VBIAS=GND over temperature | IqSleep_VDD | | | 125 | µA | Sleep mode, VBIAS = GND, -40°C ≤ TJ ≤ 125°C | 5 |
| Quiescent current PWM mode, VBIAS=5V | IqPWM_VB | | 0.16 | 0.23 | mA | PWM mode, VBIAS = 5 V, FPWM = 2 V | 5 |
| Quiescent current PWM mode, VBIAS=GND | IqPWM_VDD | | 0.65 | 0.85 | mA | PWM mode, VBIAS = GND, FPWM = 2 V | 5 |
| Bias current sleep mode | IBIAS_Sleep | | | 33 | µA | Sleep mode, VBIAS = 5 V | 5 |
| Bias current sleep mode over temperature | IBIAS_Sleep | | | 60 | µA | Sleep mode, VBIAS = 5 V, -40°C ≤ TJ ≤ 125°C | 5 |
| Bias current PWM mode | IBIAS_PWM | | 0.5 | 0.7 | mA | PWM mode, VBIAS = 5 V | 5 |
| Feedback voltage over temperature | VFB | 1.217 | | 1.255 | V | 5 V < Vin < 38 V, -40°C ≤ TJ ≤ 125°C | 5 |
| FB bias current | IFB | -200 | | 200 | nA | VFB = 1.20 V | 5 |
| VDD pin output voltage at 5 mA | VDD | 5.99 | | | V | 7 V < Vin < 35 V, IVDD = 0 mA to 5 mA | 5 |
| VDD pin output voltage over temperature | VDD | 5.5 | | 6.5 | V | 7 V < Vin < 35 V, IVDD = 0 mA to 5 mA, -40°C ≤ TJ ≤ 125°C | 5 |
| Soft-start source current over temperature | ISS_Source | 1.5 | | 4.6 | µA | -40°C ≤ TJ ≤ 125°C | 5 |
| VBIAS on voltage | Vbias_th | 2.64 | 2.9 | 3.07 | V | Specified at IBIAS = 92.5% of full value | 5 |
| Peak current limit over temperature | ILIMPK | 3.15 | | 6.05 | A | -40°C ≤ TJ ≤ 125°C | 6 |
| PGOOD threshold over temperature | VTH_PGOOD | 89 | | 95 | % | Measured at FB, PGOOD rising, -40°C ≤ TJ ≤ 125°C | 6 |
| PGOOD hysteresis | | 2 | 6 | 8 | % | | 6 |
| UVLO threshold falling over temperature | VUVLO | 2.7 | | 3.3 | V | Vin falling, shutdown, VDD = 2.70 V, -40°C ≤ TJ ≤ 125°C | 6 |
| UVLO threshold rising over temperature | VUVLO | 3.7 | | 4.3 | V | Vin rising, soft-start, VDD = VIN, -40°C ≤ TJ ≤ 125°C | 6 |
| Enable threshold voltage over temperature | VthEN | 0.8 | | 1.4 | V | Enable rising, -40°C ≤ TJ ≤ 125°C | 6 |
| FPWM threshold over temperature | VTH_FPWM | 0.8 | | 1.6 | V | -40°C ≤ TJ ≤ 125°C | 6 |
| Error amp transconductance over temperature | gm | 400 | | 1000 | µmho | -40°C ≤ TJ ≤ 125°C | 6 |
| COMP pin voltage range | VCOMP | 0.64 | | 1.27 | V | | 6 |
| Switch on resistance over temperature | RDS(ON) | 0.04 | | 0.2 | Ω | Isw = 2A, -40°C ≤ TJ ≤ 125°C | 7 |
| Switch off state leakage over temperature | Isw_off | | | 5 | µA | Vin = 38 V, VSW = 0 V, -40°C ≤ TJ ≤ 125°C | 7 |
| Switching frequency tolerance | fsw | -10 | | 10 | % | RFREQ = 62k, 124k, 240k, -40°C ≤ TJ ≤ 125°C | 7 |
| Switching frequency range | fSW | 150 | | 500 | kHz | -40°C ≤ TJ ≤ 125°C | 7 |
| Upper frequency synchronization range | FSYNC_UP | | | 30 | % | As compared to nominal fSW, -40°C ≤ TJ ≤ 125°C | 7 |
| Lower frequency synchronization range | FSYNC_DN | -20 | | | % | As compared to nominal fSW, -40°C ≤ TJ ≤ 125°C | 7 |
| Sync pin threshold rising over temperature | VSYNC | 1.6 | | | V | SYNC rising, -40°C ≤ TJ ≤ 125°C | 7 |
| Sync pin threshold falling over temperature | VSYNC | 0.8 | | | V | SYNC falling, -40°C ≤ TJ ≤ 125°C | 7 |
| Break-before-make BOOT leakage over temperature | IBOOT | | | 5 | µA | BOOT = 6 V, SW = GND, -40°C ≤ TJ ≤ 125°C | 7 |
| Thermal shutdown threshold | TSD | | 160 | | °C | | 6 |
| Thermal resistance junction-to-ambient | θJA | | 32 | | °C/W | Power dissipation = 1W, 0 lfpm air flow | 6 |
| Junction-to-ambient thermal resistance (PWP 20 pins) | RθJA | | 25.4 | | °C/W | | 5 |
| Junction-to-case (top) thermal resistance (PWP 20 pins) | RθJC(top) | | 19.6 | | °C/W | | 5 |
| Junction-to-board thermal resistance (PWP 20 pins) | RθJB | | 16.5 | | °C/W | | 5 |
| Junction-to-case (bottom) thermal resistance (PWP 20 pins) | RθJC(bot) | | 0.8 | | °C/W | | 5 |
| Quiescent current in shutdown | ISD | | 10.8 | | µA | EN = 0 V | 5 |
| Feedback voltage | VFB | | 1.236 | | V | 5 V < Vin < 38 V | 5 |
| Output voltage line regulation | ΔVOUT/ΔVIN | | 0.00025 | | %/V | 5 V < Vin < 38 V | 5 |
| Output voltage load regulation | ΔVOUT/ΔIOUT | | 0.08 | | %/A | 0.8 V < VCOMP < 1.15 V | 5 |
| Soft-start source current | ISS_Source | | 2.5 | | µA | | 5 |
| Peak current limit | ILIMPK | | 4.7 | | A | | 6 |
| Short circuit frequency foldback threshold | VFB_SC | | 0.87 | | V | Measured at FB falling | 6 |
| Min frequency in foldback | F_min_sc | | 45 | | kHz | VFB < 0.3 V | 6 |
| PGOOD threshold | VTH_PGOOD | | 92 | | % | Measured at FB, PGOOD rising | 6 |
| PGOOD on resistance | RDS_PGOOD | | 150 | | Ω | PGOOD sink current = 500 µA | 6 |
| PGOOD leakage current | IPGOOD_HI | | 1.25 | | nA | PGOOD = 5 V | 6 |
| UVLO threshold falling | VUVLO | | 2.96 | | V | Vin falling, shutdown, VDD = 2.96 V | 6 |
| UVLO threshold rising | VUVLO | | 3.99 | | V | Vin rising, soft-start, VDD = VIN | 6 |
| Enable threshold voltage | VthEN | | 1.18 | | V | Enable rising | 6 |
| Enable hysteresis | | | 180 | | mV | | 6 |
| EN source current | IEN_Source | | 4.85 | | µA | EN = 0 V | 6 |
| FPWM threshold | VTH_FPWM | | 1.24 | | V | | 6 |
| Error amp transconductance | gm | | 675 | | µmho | | 6 |
| COMP source current | ICOMP | | 57 | | µA | VCOMP = 0.9 V | 6 |
| COMP sink current | ICOMP | | 57 | | µA | VCOMP = 0.9 V | 6 |
| Switch on resistance | RDS(ON) | | 0.095 | | Ω | Isw = 2A | 7 |
| Switch off state leakage current | Isw_off | | 0.002 | | µA | Vin = 38 V, VSW = 0 V | 7 |
| FREQ voltage | VFREQ | | 1 | | V | | 7 |
| Sync pin threshold rising | VSYNC | | 1.23 | | V | SYNC rising | 7 |
| Sync pin threshold falling | VSYNC | | 1.1 | | V | SYNC falling | 7 |
| Sync pin hysteresis | | | 135 | | mV | | 7 |
| SYNC leakage current | ISYNC | | 2 | | nA | | 7 |
| Minimum off-time | TOFFMIN | | 300 | | ns | | 7 |
| Minimum on-time | TONMIN | | 190 | | ns | | 7 |
| Sleep mode threshold hysteresis | THSLEEP_HYS | | 101.3 | | % | VFB rising, % of THWAKE | 7 |
| Wake up threshold | THWAKE | | 1.236 | | V | Measured at falling FB, COMP = 0.6 | 7 |
| BOOT pin leakage current | IBOOT | | 0.001 | | µA | BOOT = 6 V, SW = GND | 7 |
## CAD (KiCad official)
- Symbol: `LM26003MHX`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP (KiCad packages3D, STEP)
- 3D model files: `lm26003mhx-etched.step` / `lm26003mhx-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm26003mhx.step` / `lm26003mhx.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/lm26003.pdf) (35 pp, sha256 `e141f2bc565d916a`, retrieved 2026-11-05, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm26003mhx-datasheet.pdf)