component
LM25141QRGETQ1
Public Made by Adomby adom
Texas Instruments DC-DC Converters, VQFN-24-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LM25141QRGETQ1
Texas Instruments · DC-DC Converters · VQFN-24-EP(4x4)
LM25141QRGETQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DEMB | input | Diode emulation pin enabling diode emulation when connected to AGND, forced PWM mode when connected to VDDA, or external clock synchronization input. |
| 2 | VDDA | power_out | Internal analog bias regulator output requiring a capacitor connection from VDDA to AGND. |
| 3 | AGND | power_in | Analog ground connection providing ground return for internal voltage reference and analog circuits. |
| 4 | RT | input | Oscillator frequency adjustment pin using resistor-to-ground for frequency range 2.2 MHz (1.8-2.53 MHz) or 440 kHz (300-500 kHz), with analog voltage adjustment through resistor also supported. |
| 5 | DITH | output | Dither output charged and discharged with 20-µA current source modulating oscillator frequency between -5% and +5%, disabled by connecting to VDDA. |
| 6 | OSC | input | Frequency selection pin setting oscillator to 2.2 MHz when connected to VDDA or 440 kHz when connected to AGND. |
| 7 | LOL | output | Low-side gate driver turnoff output. |
| 8 | LO | output | Low-side gate driver turnon output. |
| 9 | PGND | power_in | Power ground connection pin for low-side NMOS gate driver. |
| 10 | VCC | power_in | VCC bias supply pin requiring a capacitor connection from VCC to PGND. |
| 11 | HB | power_in | High-side driver supply pin for bootstrap gate drive. |
| 12 | SW | passive | Switching node of the buck regulator connecting to bootstrap capacitor, source terminal of high-side MOSFET, and drain terminal of low-side MOSFET. |
| 13 | HO | output | High-side gate driver turnon output. |
| 14 | HOL | output | High-side gate driver turnoff output. |
| 15 | VIN | power_in | Supply voltage input source for VCC regulator, operating from 3.8 V to 42 V. |
| 16 | VCCX | power_in | Optional external bias supply input internally connected to VCC when above 4.5 V with internal regulator disabled; must be grounded if unused. |
| 17 | VOUT | input | Current sense amplifier input connected to output side of current sense resistor. |
| 18 | CS | input | Current sense amplifier input requiring low current Kelvin connection to inductor side of external current sense resistor. |
| 19 | FB | input | Feedback pin connected to VDDA for 3.3 V fixed output, to AGND for 5 V fixed output, or to output divider network for 1.5-15 V adjustable output with 1.2 V regulation threshold. |
| 20 | COMP | input | Output of the transconductance error amplifier. |
| 21 | PG | tri_state | Open-collector output switching low when VOUT is outside power good window. |
| 22 | SS | input | Soft-start programming pin with external capacitor and internal 20-µA current source setting ramp rate, turning off gate driver outputs when pulled below 80 mV. |
| 23 | EN | input | An active high logic input enabling the controller. |
| 24 | RES | output | Restart timer pin with external capacitor configuring hiccup mode current limiting, determining off-time before automatic restart after 512 consecutive PWM cycles with cycle-by-cycle current limiting. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
CAD (KiCad official)
- Symbol:
LM25141QRGETQ1 - Footprint:
Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm - 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
lm25141qrgetq1-etched.step/lm25141qrgetq1-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm25141qrgetq1.step/lm25141qrgetq1.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (55 pp, sha256
4e8600680b2accdb, retrieved 2026-10-01, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM25141QRGETQ1
**Texas Instruments** · DC-DC Converters · VQFN-24-EP(4x4)
LM25141QRGETQ1 from Texas Instruments, in a VQFN-24-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | DEMB | input | Diode emulation pin enabling diode emulation when connected to AGND, forced PWM mode when connected to VDDA, or external clock synchronization input. |
| 2 | VDDA | power_out | Internal analog bias regulator output requiring a capacitor connection from VDDA to AGND. |
| 3 | AGND | power_in | Analog ground connection providing ground return for internal voltage reference and analog circuits. |
| 4 | RT | input | Oscillator frequency adjustment pin using resistor-to-ground for frequency range 2.2 MHz (1.8-2.53 MHz) or 440 kHz (300-500 kHz), with analog voltage adjustment through resistor also supported. |
| 5 | DITH | output | Dither output charged and discharged with 20-µA current source modulating oscillator frequency between -5% and +5%, disabled by connecting to VDDA. |
| 6 | OSC | input | Frequency selection pin setting oscillator to 2.2 MHz when connected to VDDA or 440 kHz when connected to AGND. |
| 7 | LOL | output | Low-side gate driver turnoff output. |
| 8 | LO | output | Low-side gate driver turnon output. |
| 9 | PGND | power_in | Power ground connection pin for low-side NMOS gate driver. |
| 10 | VCC | power_in | VCC bias supply pin requiring a capacitor connection from VCC to PGND. |
| 11 | HB | power_in | High-side driver supply pin for bootstrap gate drive. |
| 12 | SW | passive | Switching node of the buck regulator connecting to bootstrap capacitor, source terminal of high-side MOSFET, and drain terminal of low-side MOSFET. |
| 13 | HO | output | High-side gate driver turnon output. |
| 14 | HOL | output | High-side gate driver turnoff output. |
| 15 | VIN | power_in | Supply voltage input source for VCC regulator, operating from 3.8 V to 42 V. |
| 16 | VCCX | power_in | Optional external bias supply input internally connected to VCC when above 4.5 V with internal regulator disabled; must be grounded if unused. |
| 17 | VOUT | input | Current sense amplifier input connected to output side of current sense resistor. |
| 18 | CS | input | Current sense amplifier input requiring low current Kelvin connection to inductor side of external current sense resistor. |
| 19 | FB | input | Feedback pin connected to VDDA for 3.3 V fixed output, to AGND for 5 V fixed output, or to output divider network for 1.5-15 V adjustable output with 1.2 V regulation threshold. |
| 20 | COMP | input | Output of the transconductance error amplifier. |
| 21 | PG | tri_state | Open-collector output switching low when VOUT is outside power good window. |
| 22 | SS | input | Soft-start programming pin with external capacitor and internal 20-µA current source setting ramp rate, turning off gate driver outputs when pulled below 80 mV. |
| 23 | EN | input | An active high logic input enabling the controller. |
| 24 | RES | output | Restart timer pin with external capacitor configuring hiccup mode current limiting, determining off-time before automatic restart after 512 consecutive PWM cycles with cycle-by-cycle current limiting. |
| 25 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | VQFN-24-EP(4x4) |
| Category | Power Management (PMIC) |
| Pins | 25 |
## CAD (KiCad official)
- Symbol: `LM25141QRGETQ1`
- Footprint: `Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm`
- 3D model: VQFN-24-EP(4x4) (KiCad packages3D, STEP)
- 3D model files: `lm25141qrgetq1-etched.step` / `lm25141qrgetq1-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm25141qrgetq1.step` / `lm25141qrgetq1.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/cn/lit/gpn/lm25141-q1) (55 pp, sha256 `4e8600680b2accdb`, retrieved 2026-10-01, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm25141qrgetq1-datasheet.pdf)