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LM25141QRGERQ1

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Texas Instruments DC-DC Converters, VQFN-24(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management (pmic)lm25141qrgerq1factory-2.0.0extractor-text
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Contents

README

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LM25141QRGERQ1

Texas Instruments · DC-DC Converters · VQFN-24(4x4)

LM25141QRGERQ1 from Texas Instruments, in a VQFN-24(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DEMB input Diode emulation pin; connect to AGND to enable diode emulation or to VDDA for Forced PWM mode; can also synchronize internal oscillator to external clock in 350-550 kHz (440 kHz mode) or 1.8-2.6 MHz range (2.2 MHz mode).
2 VDDA power_out Internal analog bias regulator output (typ. 5 V, UVLO 3.2 V); requires ceramic bypass capacitor (≥100 nF) from VDDA to AGND.
3 AGND power_in Analog ground connection and return for internal voltage reference and analog circuits; connect exposed thermal pad to AGND and PGND.
4 RT input Oscillator frequency trim pin; resistor to ground shifts frequency from 2.2 MHz (1.8-2.53 MHz range) or 440 kHz (300-500 kHz range), or apply analog voltage (0-0.6 V) through resistor to modulate frequency.
5 DITH output Dither/frequency modulation output; capacitor to AGND charged/discharged by internal 20-µA source creates triangular waveform (1.14-1.26 V) modulating oscillator ±5%; disabled by connecting to VDDA.
6 OSC input Oscillator frequency selection pin; connect to VDDA for 2.2 MHz operation (2.1-2.3 kHz typ.) or to AGND for 440 kHz operation (420-460 kHz typ.); latched during VCC power-up.
7 LOL output Low-side gate driver turnoff output (pulldown); drives low-side MOSFET gate with 100 mA sink current, 0.05 V low output, <3 ns fall time.
8 LO output Low-side gate driver turnon output (pullup); drives low-side MOSFET gate with 3.25 A source current, 0.07 V high output, <4 ns rise time.
9 PGND power_in Power ground connection for low-side NMOS gate driver; must connect to PCB power ground plane; PGND to AGND voltage range -0.3 to +0.3 V.
10 VCC power_out VCC bias supply output (nom. 5 V, range 4.75-5.25 V, UVLO 3.4 V); requires 2.2-4.7 µF bypass capacitor to PGND with 75 mA source current limit.
11 HB power_out High-side bootstrap supply pin (0-5.25 V from SW); external bootstrap capacitor (0.1-0.47 µF ceramic, low-ESR) charged through bootstrap diode from VCC when SW low; UVLO threshold 2.5 V.
12 SW passive Switching node connection of buck regulator; connects to high-side MOSFET source, low-side MOSFET drain, and bootstrap capacitor between SW and HB; operates between GND and VIN (-0.3 to +47 V absolute maximum).
13 HO output High-side gate driver turnon output (pullup relative to SW); drives high-side MOSFET gate with 3.25 A peak source current, 0.07 V high output, <4 ns rise time.
14 HOL output High-side gate driver turnoff output (pulldown from HB to SW); pulls high-side gate low with 4.25 A peak sink current, 0.05 V low output, <3 ns fall time.
15 VIN power_in Supply voltage input (3.8-42 V steady-state, 47 V absolute maximum including transients); input to internal VCC regulator; requires high-quality bypass capacitor to minimize ringing.
16 VCCX power_in Optional external bias supply input (0-6.5 V); if VCCX >4.5 V, internally connected to VCC and internal regulator disabled; must be grounded to PGND if unused.
17 VOUT input Current sense amplifier noninverting input (1.5-15 V); connect to output side of external current sense resistor with low impedance Kelvin connection for <40 ns amplifier delay.
18 CS input Current sense amplifier inverting input; make low-current Kelvin connection to inductor side of external current sense resistor; 75 mV threshold (±0.9%) for cycle-by-cycle current limit with 12 V/V gain.
19 FB input Feedback voltage pin; connect to VDDA for fixed 3.3-V output (3.273-3.327 V), to AGND for fixed 5-V output (4.96-5.04 V), or to resistor divider for adjustable 1.5-15 V output with 1.2 V regulation threshold.
20 COMP input Compensation amplifier output pin for external error amplifier feedback network; transconductance amplifier input with 1200 µS typical gain and 1 V full-scale input range.
21 PG output Power good open-collector output; switches low (<0.4 V at 2 mA sink) when VOUT falls below 92% or rises above 110% of regulation voltage with 25-µs overvoltage and 30-µs undervoltage filter delays.
22 SS input Soft-start programming pin; external capacitor and internal 20-µA current source control error amplifier ramp rate during startup; pulling below 80 mV disables gate driver outputs while maintaining other functions.
23 EN input Active-high logic enable input (0-47 V range); controller enabled when >2 V, shutdown mode (<10 µA IQ) when <0.8 V; logic input leakage <1 µA.
24 RES output Hiccup restart timer pin; external capacitor (20-µA source current, 1.2 V threshold, 4 Ω pulldown) sets recovery delay after 512 consecutive current-limit cycles; grounding to VDD during power-up disables hiccup protection.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package VQFN-24(4x4)
Category Power Management (PMIC)
Pins 25

CAD (KiCad official)

  • Symbol: LM25141QRGERQ1
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x4mm_P0.5mm_EP2.6x2.6mm
  • 3D model: VQFN-24(4x4) (KiCad packages3D, STEP)
  • 3D model files: lm25141qrgerq1-etched.step / lm25141qrgerq1-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm25141qrgerq1.step / lm25141qrgerq1.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (55 pp, sha256 4e8600680b2accdb, retrieved 2026-09-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.2, primary claude-haiku-4-5-20251001 (text), consensus claude-sonnet-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF