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LM25066IAPSQ

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Texas Instruments Surge Suppressors, WQFN-24(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM25066IAPSQ

Texas Instruments · Surge Suppressors · WQFN-24(4x5)

LM25066IAPSQ from Texas Instruments, in a WQFN-24(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 ADR2 input SMBus address line 2, a 3-state address line to be connected to GND, VDD, or left floating.
2 ADR1 input SMBus address line 1, a 3-state address line to be connected to GND, VDD, or left floating.
3 ADR0 input SMBus address line 0, a 3-state address line to be connected to GND, VDD, or left floating.
4 VDD power_out Internally sub-regulated 4.5V bias supply output; connect a 1 µF capacitor to ground for bypassing.
5 CL input Current limit range select: GND sets the nominal over-current threshold to 25mV, VDD sets it to 46mV.
6 CB input Circuit breaker range select: GND sets the trip point to 1.8 times the over-current threshold, VDD sets it to 3.6 times.
7 FB input Power Good feedback input; an external divider from OUT sets the PGD switching voltage with a 1.167V threshold and 24 µA hysteresis current source.
8 RETRY input Fault retry input: grounded continually retries power-up during a fault, connected to VDD latches off during a fault.
9 TIMER passive External capacitor pin that sets the insertion time delay, fault timeout period and restart timing.
10 PWR passive Power limit set; an external resistor, with the sense resistor RS, sets the maximum power dissipation allowed in the external MOSFET.
11 PGD output Open-drain Power Good output, high when FB is above 1.167V and the input supply is within its under- and over-voltage thresholds; needs a pullup resistor.
12 OUT input Output feedback connected to the external MOSFET source, used to determine MOSFET VDS for power limiting and to monitor the output voltage.
13 GATE output Gate drive output connected to the external MOSFET's gate.
14 SENSE input Current sense input; the voltage across RS is measured from VIN to this pin and triggers current limit and the fault timer at the over-current threshold.
15 VIN power_in Positive supply input (2.9V to 17V operating); a small ceramic bypass capacitor close to the pin is recommended.
16 UVLO/EN input Under-voltage lockout input with 1.16V enable threshold and 23 µA hysteresis current source; also usable for remote shutdown.
17 OVLO input Over-voltage lockout input with 1.16V disable threshold and 23 µA hysteresis current source set by an external divider.
18 GND power_in Circuit ground.
19 SDA bidirectional SMBus data pin.
20 SCL input SMBus clock pin.
21 SMBA output SMBus alert pin, active low.
22 VREF power_out Internally generated precision 2.73V reference for analog to digital conversion; connect a 1 µF capacitor to ground.
23 DIODE passive Connect to a diode-configured NPN transistor for temperature monitoring.
24 VAUX input Auxiliary voltage input for telemetry from an external source, full scale input of 1.16V.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package WQFN-24(4x5)
Category TVS/Fuse/Board Level Protection
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VIN, SENSE to GND -0.3 24 V 4
GATE, FB, UVLO/EN, OVLO, PGD to GND -0.3 20 V 4
OUT to GND -1 20 V 4
SCL, SDA, SMBA, CL, CB, ADR0-2, VDD, VAUX, DIODE, RETRY to GND -0.3 6 V 4
VIN to SENSE -0.3 0.3 V 4
ESD Human Body Model 2 kV 100 pF through 1.5 kΩ 4
Storage Temperature -65 150 °C 4
Junction Temperature TJ 150 °C 4
VIN, SENSE, OUT voltage 2.9 17 V 4
VDD VDD 2.9 5.5 V 4
Junction Temperature TJ -40 125 °C 4
Input Current, enabled IIN-EN 5.8 8 mA UVLO = 2V and OVLO = 0.7V 4
Power On Reset threshold at VIN POR 2.6 2.8 V VIN increasing 4
VDD regulator voltage VDD 4.3 4.5 4.7 V IVDD = 5mA, VIN = 12V 4
VDD regulator voltage VDD 3.5 3.9 4.3 V IVDD = 5mA, VIN = 4.5V 4
VDD Current Limit VDDILIM 25 45 mA 4
UVLO threshold UVLOTH 1.147 1.16 1.173 V VUVLO Falling 4
UVLO hysteresis current UVLOHYS 18 23 28 µA UVLO = 1V 4
UVLO bias current UVLOBIAS 1 µA UVLO = 3V 4
OVLO threshold OVLOTH 1.141 1.16 1.185 V VOVLO rising 4
OVLO hysteresis current OVLOHYS -28 -23 -18 µA OVLO = 1V 4
OVLO bias current OVLOBIAS 1 µA OVLO = 1V 4
PGD Output low voltage PGDVOL 25 60 mV ISINK = 2 mA 4
PGD Off leakage current PGDIOH 1 µA VPGD = 17V 4
FB Threshold FBTH 1.141 1.167 1.19 V VFB rising 5
FB Hysteresis Current FBHYS -31 -24 -18 µA 5
FB Off Leakage Current FBLEAK 1 µA VFB = 1V 5
Power limit sense voltage (VIN-SENSE) PWRLIM 9 12.5 15 mV SENSE-OUT = 12V, RPWR = 25 kΩ 5
GATE Source current IGATE -28 -22 -16 µA Normal operation 5
GATE Fault Sink current IGATE 1.5 2 2.5 mA UVLO = 1V 5
GATE POR Circuit Breaker sink current IGATE 105 190 275 mA VIN - SENSE = 150 mV or VIN < RPOR, VGATE = 5V 5
Gate output voltage in normal operation VGATE 17 18.8 20.3 V GATE voltage with respect to ground 5
OUT bias current, enabled IOUT-EN 16 µA OUT = VIN, normal operation 5
Current limit threshold voltage VCL 22.5 25 27.5 mV CL = GND 5
Current limit threshold voltage VCL 23 25 27 mV CL = GND, TJ = 10°C to 85°C 5
Current limit threshold voltage VCL 41 46 52 mV CL = VDD 5
Circuit breaker threshold voltage x 1.8 VCB 35 45 55 mV VIN - SENSE, CL = GND, CB = GND 5
CB:CL Ratio CB:CL 1.6 1.8 2 CB = GND 5
Circuit breaker threshold voltage x 3.6 VCB 70 90 110 mV VIN - SENSE, CL = GND, CB = VDD 5
CB:CL Ratio CB:CL 3.1 3.6 4 CB = VDD 5
Circuit breaker response time tCB 0.6 1.2 µs VIN - SENSE stepped from 0 mV to 150 mV, time to GATE low, no load 5
TIMER Upper threshold VTMRH 1.54 1.7 1.85 V 5
TIMER Lower threshold VTMRL 0.85 1 1.07 V Restart cycles 5
TIMER Insertion time current ITIMER -8 -5.5 -3 µA TIMER pin = 2V 5
TIMER Sink current, end of insertion time ITIMER 1.4 1.9 2.4 mA 5
TIMER Fault detection current ITIMER -120 -90 -60 µA 5
Reference Voltage VREF 2.703 2.73 2.757 V 6
Input Current Accuracy (LM25066IA) IINACC -1 1 % VIN, SENSE = 25mV, CL = GND, TJ = 10°C to 85°C 7
Input Current Accuracy (LM25066IA) IINACC -1.2 1 % VIN, SENSE = 25mV, CL = GND 7
Input Current Accuracy (LM25066IA) IINACC -1.8 1.8 % VIN, SENSE = 50mV, CL = VDD 7
Input Current Accuracy (LM25066IA) IINACC -5 5 % VIN- SENSE= 5mV, CL= GND, TJ = 10°C to 85°C 7
VAUX, VIN, VOUT Accuracy (LM25066IA) VACC -1 1 % VIN, VOUT = 12V, VAUX = 1V, TJ = 10°C to 85°C 7
VAUX, VIN, VOUT Accuracy (LM25066IA) VACC -1 1.2 % VIN, VOUT = 12V, VAUX = 1V 7
Input Power Accuracy (LM25066IA) PINACC -2 2 % VIN = 12V, VIN, SENSE = 25mV, CL = GND 7
Temperature Accuracy Using Local Diode TACC 2 10 °C TA = 10°C to 85°C 7
External Diode Current Source, high level IDIODE 250 300 µA High level 7
Data, Clock Input Low Voltage VIL 0.8 V 7
Data, Clock Input High Voltage VIH 2.1 5.5 V 7
Data Output Low Voltage VOL 0 0.4 V IPULLUP = 4mA 7
Input Leakage Current ILEAK 1 µA SDA, SMBA, SCL = 5V 7
Junction to Ambient θJA 42.3 °C/W 4-layer, 4"x3", 2/1/1/2 oz. Cu board per JEDEC 7
Junction to Case θJC 9.5 °C/W 7

CAD (KiCad official)

  • Symbol: LM25066IAPSQ
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: WQFN-24(4x5) (KiCad packages3D, STEP)
  • 3D model files: lm25066iapsq-etched.step / lm25066iapsq-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm25066iapsq.step / lm25066iapsq.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (59 pp, sha256 5b8c3f70d3e0661f, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF