component
LM25061PMMX-2
Public Made by Adomby adom
Texas Instruments Surge Protection Devices (SPDs), MSOP-10. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM25061PMMX-2
Texas Instruments · Surge Protection Devices (SPDs) · MSOP-10
LM25061PMMX-2 from Texas Instruments, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SENSE | input | Current sense input: the voltage across the current sense resistor RS is measured from VIN to this pin, and if it reaches 50 mV the load current is limited and the fault timer activates. |
| 2 | VIN | power_in | Positive supply input within the 2.9 V to 17 V operating range, with a small ceramic bypass capacitor placed close to the pin recommended to suppress transients when the load current is switched off. |
| 3 | UVLO/EN | input | Under-voltage lockout and enable pin: an external divider from the input sets the turn-on threshold, the enable threshold at the pin is 1.17 V, an internal 20 µA source provides hysteresis, and the pin can be used for remote shutdown. |
| 4 | FB | input | Output feedback: an external divider from the output sets the voltage at which the PGD pin switches, the threshold at the pin is 1.17 V, and an internal 22 µA current source provides hysteresis. |
| 5 | GND | power_in | Circuit ground reference for the controller. |
| 6 | TIMER | passive | Timing capacitor pin: an external capacitor sets the insertion time delay and the fault timeout period, and also sets the restart timing of the LM25061-2. |
| 7 | PWR | input | Power limit set: an external resistor connected here, together with the current sense resistor RS, sets the maximum power dissipation allowed in the external series pass MOSFET. |
| 8 | PGD | output | Open-drain Power Good output that is high when the voltages at the FB and UVLO pins are above their thresholds; PGD off voltage is rated 0 V to 17 V. |
| 9 | OUT | input | Output feedback: connect to the output rail (external MOSFET source), where it is used internally to determine the MOSFET VDS for power limiting. |
| 10 | GATE | output | Gate drive output for the external N-channel MOSFET gate, with the pin voltage limited to 19.5 V above ground. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | MSOP-10 |
| Category | Circuit Protection |
| Pins | 10 |
CAD (KiCad official)
- Symbol:
LM25061PMMX-2 - Footprint:
Package_SO:MSOP-10_3x3mm_P0.5mm - 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files:
lm25061pmmx-2-etched.step/lm25061pmmx-2-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm25061pmmx-2.step/lm25061pmmx-2.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
c9d167fe4f4f2fbc, retrieved 2026-10-08, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).