Loads when you scroll to it. Unloads after 5 minutes in the background.

Symbol & Footprint

Schematic Symbol

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.

PCB Footprint

Open full view ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Loads when you scroll to it. Unloads after 5 minutes in the background.
Download PDF
Contents

README

markdown

LM224ADT

STMicroelectronics · Operational Amplifier · SOIC-14

LM224ADT from STMicroelectronics, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Output of op-amp channel 1. Class-AB output stage; short-circuit current limited to ~40 mA. Do not short to VCC when VCC > 15 V (destructive dissipation possible).
2 IN1- input Inverting input of op-amp channel 1. Typical input bias current 20 nA, input offset current 2 nA. Do not drive below -0.3 V (input parasitic NPN action).
3 IN1+ input Non-inverting input of op-amp channel 1. Common-mode input range includes ground; upper limit is VCC - 1.5 V.
4 VCC+ power_in Positive supply rail. Single-supply operation 3 V to 30 V, or split-supply +1.5 V to +15 V. Absolute maximum ±16 V (single) or 32 V (single-supply). Total supply current typically 375 μA per amplifier.
5 IN2+ input Non-inverting input of op-amp channel 2. Common-mode input range includes ground.
6 IN2- input Inverting input of op-amp channel 2. Typical input bias current 20 nA.
7 OUT2 output Output of op-amp channel 2. Class-AB output stage; short-circuit current limited to ~40 mA.
8 OUT3 output Output of op-amp channel 3. Class-AB output stage; short-circuit current limited to ~40 mA.
9 IN3- input Inverting input of op-amp channel 3. Typical input bias current 20 nA.
10 IN3+ input Non-inverting input of op-amp channel 3. Common-mode input range includes ground.
11 VCC- power_in Negative supply rail / ground. Tie to GND for single-supply operation, or to negative rail (down to -15 V) for split-supply operation.
12 IN4+ input Non-inverting input of op-amp channel 4. Common-mode input range includes ground.
13 IN4- input Inverting input of op-amp channel 4. Typical input bias current 20 nA.
14 OUT4 output Output of op-amp channel 4. Class-AB output stage; short-circuit current limited to ~40 mA.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package SOIC-14
Category Op-amp/Cmp
Pins 14

Ordering variants

Same part, different packaging or reel option.

  • LM224ADT
  • LM224DT
  • LM224WDT
  • LM224ADTLM124DT
  • LM224APT
  • LM224PT
  • LM224WPT
  • LM224ADTLM324APT
  • LM224ADTLM324PT
  • LM224ADTLM324WPT
  • LM224ADTLM324AWPT
  • LM224QT
  • LM224ADTLM324QT

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage (absolute maximum) VCC 32 V Printed as ±16 or 32 5
Input voltage (absolute maximum) Vi -0.3 V Printed as -0.3 to VCC + 0.3 V; upper limit VCC + 0.3 V 5
Differential input voltage (absolute maximum) Vid 32 V 5
Power dissipation, D suffix Ptot 400 mW D suffix 5
Input current Iin 50 mA Input driven negative 5
Storage temperature range Tstg -65 150 °C 5
Maximum junction temperature Tj 150 °C 5
Thermal resistance junction to ambient, SO14 Rthja 103 °C/W SO14, single layer board 5
Thermal resistance junction to case, SO14 Rthjc 31 °C/W SO14 5
ESD HBM (LM224A) HBM 800 V Human body model; row for LM224A, LM324A 5
ESD MM MM 100 V Machine model 5
ESD CDM CDM 1500 V Charged device model 5
Supply voltage, single supply VCC 3 30 V Single supply 6
Supply voltage, dual supply VCC 1.5 15 V Dual supply (±1.5 to ±15 V) 6
Common-mode input voltage range VICM -0.1 -1 V Printed as (VCC-) - 0.1 to (VCC+) - 1; referenced to supply rails 6
Operating temperature range, LM224 TOper -40 105 °C LM224 row 6
Input offset voltage (LM224A) Vio 2 3 mV Tamb = 25 °C 7
Input offset voltage (LM224A) Vio 5 mV Tmin ≤ Tamb ≤ Tmax 7
Input offset current Iio 2 20 nA Tamb = 25 °C 7
Input offset current Iio 40 nA Tmin ≤ Tamb ≤ Tmax 7
Input bias current Iib 20 100 nA Tamb = 25 °C 7
Input bias current Iib 200 nA Tmin ≤ Tamb ≤ Tmax 7
Large signal voltage gain Avd 50 100 V/mV VCC+ = 15 V, RL = 2 kΩ, Vo = 1.4 V to 11.4 V, Tamb = 25 °C 7
Large signal voltage gain Avd 25 V/mV Tmin ≤ Tamb ≤ Tmax 7
Supply voltage rejection ratio SVR 65 110 dB Rs ≤ 10 kΩ, VCC+ = 5 V to 30 V, Tamb = 25 °C 7
Supply voltage rejection ratio SVR 65 dB Rs ≤ 10 kΩ, VCC+ = 5 V to 30 V, Tmin ≤ Tamb ≤ Tmax 7
Supply current, all amps, no load ICC 0.7 1.2 mA Tamb = 25 °C, VCC = 5 V 7
Supply current, all amps, no load ICC 1.5 3 mA Tamb = 25 °C, VCC = 30 V 7
Supply current, all amps, no load ICC 0.8 1.2 mA Tmin ≤ Tamb ≤ Tmax, VCC = 5 V 7
Input common mode voltage range Vicm 0 28.5 V VCC = 30 V, Tamb = 25 °C 7
Input common mode voltage range Vicm 0 28 V VCC = 30 V, Tmin ≤ Tamb ≤ Tmax 7
Common mode rejection ratio CMR 70 80 dB Rs ≤ 10 kΩ, Tamb = 25 °C 7
Common mode rejection ratio CMR 60 dB Rs ≤ 10 kΩ, Tmin ≤ Tamb ≤ Tmax 7
Output current source Isource 20 40 70 mA Vid = 1 V, VCC = 15 V, Vo = 2 V 7
Output sink current Isink 10 20 mA Vid = -1 V, VCC = 15 V, Vo = 2 V 7
Output sink current Isink 12 50 µA Vid = -1 V, VCC = 15 V, Vo = 0.2 V 7
High level output voltage VOH 26 27 V VCC = 30 V, RL = 2 kΩ, Tamb = 25 °C 7
High level output voltage VOH 26 V VCC = 30 V, RL = 2 kΩ, Tmin ≤ Tamb ≤ Tmax 7
High level output voltage VOH 27 28 V VCC = 30 V, RL = 10 kΩ, Tamb = 25 °C 7
High level output voltage VOH 27 V VCC = 30 V, RL = 10 kΩ, Tmin ≤ Tamb ≤ Tmax 7
High level output voltage VOH 3.5 V VCC = 5 V, RL = 2 kΩ, Tamb = 25 °C 7
High level output voltage VOH 3 V VCC = 5 V, RL = 2 kΩ, Tmin ≤ Tamb ≤ Tmax 7
Low level output voltage VOL 5 20 mV RL = 10kΩ, Tamb = 25 °C 8
Low level output voltage VOL 20 mV RL = 10kΩ, Tmin ≤ Tamb ≤ Tmax 8
Input offset voltage drift DVio 7 30 µV/°C 8
Input offset current drift DIio 10 200 pA/°C 8

CAD (KiCad official)

  • Symbol: LM224ADT
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: lm224adt-etched.step / lm224adt-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm224adt.step / lm224adt.glb are the bare package body.

3D model downloads

Two STEP files. Same geometry, different body top:

File Size Use it when
lm224adt.step 195 KB You want the bare part, or you mark your own boards.
lm224adt-etched.step 1.7 MB You want the part with LM224ADT already on it.

The marking in the etched file is real recessed geometry cut into the solid, not a texture or a decal: 452 faces against 237 in the bare model. It survives export, section views, and rendering in any CAD tool, and it drops straight into KiCad or Fusion with no extra setup.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (21 pp, sha256 7d935f64f066d5e4, retrieved 2026-08-17, tier: manufacturer)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF