# LM2104DR

**Texas Instruments** · Gate Drivers · SOIC-8

LM2104DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GVDD | power_in | Gate driver positive supply rail (9 V to 18 V recommended), to be locally decoupled to ground with a low ESR and ESL capacitor placed as close to the IC as possible. |
| 2 | IN | input | Control input compatible with TTL and CMOS input thresholds. |
| 3 | SD | input | Inverting shutdown control input compatible with TTL and CMOS thresholds; when pulled low it turns off both GH and GL outputs. |
| 4 | GND | power_in | Ground; all signals are referenced to this ground. |
| 5 | GL | output | Low-side gate driver output, connected to the gate of the low-side MOSFET or one end of an external gate resistor. |
| 6 | SH | passive | High-side source connection to the negative terminal of the bootstrap capacitor and the source of the high-side MOSFET, rated -1 V DC and -19.5 V for repetitive pulses under 100 ns. |
| 7 | GH | output | High-side gate driver output, connected to the gate of the high-side MOSFET or one end of an external gate resistor. |
| 8 | BST | power_in | High-side gate driver positive supply rail (107 V absolute maximum) with the bootstrap capacitor connected between BST and SH, placed as close to the IC as possible. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | SOIC-8 |
| Category | Motor Driver ICs |
| Pins | 8 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Low-side supply voltage | VGVDD | -0.3 |  | 19.5 | V |  | 4 |
| High-side supply voltage | VBST to VSH | -0.3 |  | 19.5 | V |  | 4 |
| Input voltages on IN and SD | VIN, VSD | -0.3 |  | 19.5 | V |  | 4 |
| Voltage on SH DC | VSH | -1 |  | 95 | V | DC | 4 |
| Voltage on SH repetitive pulse | VSH | -19.5 |  | 95 | V | Repetitive pulse < 100 ns | 4 |
| Voltage on BST | VBST |  |  | 107 | V |  | 4 |
| Junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Storage temperature | Tstg | -65 |  | 150 | °C |  | 4 |
| ESD HBM | V(ESD) | -1000 |  | 1000 | V | Human-body model, ANSI/ESDA/JEDEC JS-001 | 4 |
| ESD CDM | V(ESD) | -250 |  | 250 | V | Charged-device model, JESD22-C101 | 4 |
| Supply voltage | VGVDD | 9 | 12 | 18 | V |  | 4 |
| Input voltage range | VIN, VSD | 0 |  |  | V |  | 4 |
| Voltage on BST | VBST |  |  | 105 | V |  | 4 |
| Voltage on SH (DC) | VSH | -1 |  |  | V | DC | 4 |
| Voltage on SH (repetitive pulse) | VSH | -18 |  |  | V | Repetitive pulse < 100 ns | 4 |
| Voltage slew rate on SH | SRSH |  |  | 50 | V/ns |  | 4 |
| Operating junction temperature | TJ | -40 |  | 125 | °C |  | 4 |
| Input voltage high threshold IN | VHIT_IN | 1.45 |  | 2 | V | -40°C to 125°C | 5 |
| Input voltage high threshold SD | VHIT_SD | 1.45 |  | 2 | V | -40°C to 125°C | 5 |
| Input voltage low threshold IN | VLIT_IN | 0.8 |  | 1.3 | V | -40°C to 125°C | 5 |
| Input voltage low threshold SD | VLIT_SD | 0.8 |  | 1.3 | V | -40°C to 125°C | 5 |
| GVDD rising threshold | VGVDDR | 8.15 |  | 8.75 | V | VGVDDR = VGVDD - GND, -40°C to 125°C | 5 |
| GVDD falling threshold | VGVDDF | 6.75 |  | 7.7 | V | VGVDDF = VGVDD - GND, -40°C to 125°C | 5 |
| BST rising threshold | VBSTR | 7.6 |  | 8.5 | V | VBSTR = VBST - VSH, -40°C to 125°C | 5 |
| BST falling threshold | VBSTF | 6.25 |  | 7.15 | V | VBSTF = VBST - VSH, -40°C to 125°C | 5 |
| GVDD quiescent current | IGVDD |  | 430 |  | μA | VIN = VSD = 0 V | 5 |
| GVDD operating current | IDDO |  | 0.56 |  | mA | f = 50 kHz, CLOAD = 0 | 5 |
| Total BST quiescent current | IBST |  | 150 |  | uA | VIN = VSD = 0 V, VDD = 12 V | 5 |
| Total BST operating current | IBSTO |  | 0.16 |  | mA | f = 50 kHz, CLOAD = 0 | 5 |
| BST to GND quiescent current | IBSTS |  | 33.3 |  | μA | VSH = VBST = 95 V, GVDD = 12 V | 5 |
| BST to GND operating current | IBSTO |  | 0.07 |  | mA | f = 50 kHz, CLOAD = 0 | 5 |
| Input voltage hysteresis IN | VIHYS_IN |  | 0.15 |  | V |  | 5 |
| Input pulldown resistance IN | RIN_IN |  | 200 |  | kΩ | VIN = 3 V | 5 |
| Input pulldown resistance SD | RIN_SD |  | 200 |  | kΩ | VSD = 3 V | 5 |
| GVDD threshold hysteresis | VGVDDHYS |  | 0.45 |  | V |  | 5 |
| BST threshold hysteresis | VBSTHYS |  | 0.45 |  | V |  | 5 |
| GL low level output voltage | VGL_L |  | 0.25 |  | V | IGL = 100 mA, VGL_L = VGL, GND | 5 |
| GL high level output voltage | VGL_H |  | 0.8 |  | V | IGL = -100 mA, VGL_H = VGVDD, VGL | 5 |
| GL peak pullup current |  |  | 0.5 |  | A | VGL = 0V | 5 |
| GL peak pulldown current |  |  | 0.8 |  | A | VGL = 12V | 5 |
| GH low level output voltage | VGH_L |  | 0.25 |  | V | IGH = 100 mA, VGH_L = VGH, VSH | 5 |
| GH high level output voltage | VGH_H |  | 0.8 |  | V | IGH = -100 mA, VGH_H = VBST, VGH | 5 |
| GH peak pullup current |  |  | 0.5 |  | A | VGH = 0V | 5 |
| GH peak pulldown current |  |  | 0.8 |  | A | VGH = 12V | 5 |
| VIN rising to VGL falling | tDLRF |  | 115 |  | ns | VIN = 0 V to 3 V, CLOAD = 0 pF, SD = 3 V | 6 |
| VIN falling to VGH falling | tDHFF |  | 115 |  | ns | VIN = 3 V to 0 V, CLOAD = 0 pF, SD = 3 V | 6 |
| VIN falling to VGL rising | tDLFR |  | 600 |  | ns | VIN = 3 V to 0 V, CLOAD = 0 pF, SD = 3 V | 6 |
| VIN rising to VGH rising | tDHRR |  | 600 |  | ns | VIN = 0 V to 3 V, CLOAD = 0 pF, SD = 3 V | 6 |
| VSD falling to output falling | tSDF |  | 115 |  | ns | VSD = 3 V to 0 V, VIN = 3 V, CLOAD = 0 pF | 6 |
| VSD rising to output rising | tSDR |  | 115 |  | ns | VSD = 0 V to 3 V, VIN = 3 V, CLOAD = 0 pF | 6 |
| Internal deadtime | tDT |  | 475 |  | ns |  | 6 |
| GL rise time | tR_GL |  | 28 |  | ns | CLOAD = 1000 pF, VIN = 0-3 V, VSD = 3 V | 6 |
| GH rise time | tR_GH |  | 28 |  | ns | CLOAD = 1000 pF, VIN = 0-3 V, VSD = 3 V | 6 |
| GL fall time | tF_GL |  | 18 |  | ns | CLOAD = 1000 pF, VIN = 0-3 V, VSD = 3 V | 6 |
| GH fall time | tF_GH |  | 18 |  | ns | CLOAD = 1000 pF, VIN = 0-3 V, VSD = 3 V | 6 |
| Junction-to-ambient thermal resistance | RθJA |  | 133.2 |  | °C/W | D (SOIC) 8 pins | 4 |
| Junction-to-case (top) thermal resistance | RθJC(top) |  | 75.2 |  | °C/W | D (SOIC) 8 pins | 4 |
| Junction-to-board thermal resistance | RθJB |  | 76.7 |  | °C/W | D (SOIC) 8 pins | 4 |
| Junction-to-top characterization parameter | ψJT |  | 25.5 |  | °C/W | D (SOIC) 8 pins | 4 |
| Junction-to-board characterization parameter | ψJB |  | 75.9 |  | °C/W | D (SOIC) 8 pins | 5 |

## CAD (KiCad official)

- Symbol: `LM2104DR`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOIC-8 (KiCad packages3D, STEP)
- 3D model files: `lm2104dr-etched.step` / `lm2104dr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm2104dr.step` / `lm2104dr.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/lm2104.pdf) (28 pp, sha256 `40b1ca494d259a12`, retrieved 2026-10-22, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lm2104dr-datasheet.pdf)