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LM2101DR

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Texas Instruments , SOIC-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LM2101DR

Texas Instruments · IC · SOIC-8

LM2101DR from Texas Instruments, in a SOIC-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GVDD power_in Gate driver positive supply rail (recommended 9 V to 18 V) that must be locally decoupled to ground with a low ESR and ESL capacitor placed as close to the IC as possible.
2 INH input High-side control input compatible with TTL and CMOS input thresholds; an unused INH input must be tied to ground and not left open.
3 INL input Low-side control input compatible with TTL and CMOS input thresholds; an unused INL input must be tied to ground and not left open.
4 GND power_in Ground, to which all signals are referenced.
5 GL output Low-side gate driver output that connects to the gate of the low-side MOSFET or one end of an external gate resistor when used.
6 SH power_in High-side source connection to the negative terminal of the bootstrap capacitor and the source of the high-side MOSFET, with DC range of -1 V to 95 V absolute maximum.
7 GH output High-side gate driver output that connects to the gate of the high-side MOSFET or one end of an external gate resistor when used.
8 BST power_in High-side gate driver positive supply rail (107 V absolute maximum) that connects to the positive terminal of the bootstrap capacitor, which must be placed as close to the IC as possible.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package SOIC-8
Category
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Low-side supply voltage VGVDD -0.3 19.5 V 4
High-side supply voltage VBST to VSH -0.3 19.5 V 4
Input voltages on INL and INH VINL, VINH -0.3 19.5 V 4
Voltage on SH (DC) VSH -1 95 V DC 4
Voltage on SH (repetitive pulse) VSH -19.5 95 V Repetitive pulse < 100 ns 4
Voltage on BST VBST 107 V 4
Junction temperature TJ -40 125 °C 4
Storage temperature Tstg -65 150 °C 4
ESD human-body model V(ESD) -1000 1000 V HBM, ANSI/ESDA/JEDEC JS-001 4
ESD charged-device model V(ESD) -250 250 V CDM, JESD22-C101 4
Supply voltage VGVDD 9 12 18 V 4
Input voltage range min VINL, VINH 0 V 4
Voltage on BST VBST 105 V 4
Voltage on SH (DC) VSH -1 V DC 4
Voltage on SH (repetitive pulse) VSH -18 V Repetitive pulse < 100 ns 4
Voltage slew rate on SH SRSH 50 V/ns 4
Operating junction temperature TJ -40 125 °C 4
Input voltage high threshold VHIT 1.45 2 V -40°C to 125°C 5
Input voltage low threshold VLIT 0.8 1.3 V -40°C to 125°C 5
GVDD rising threshold VGVDDR 8.15 8.75 V VGVDDR = VGVDD - GND, -40°C to 125°C 5
GVDD falling threshold VGVDDF 6.75 7.7 V VGVDDF = VGVDD - GND, -40°C to 125°C 5
VBST rising threshold VBSTR 7.6 8.5 V VBSTR = VBST - VSH, -40°C to 125°C 5
VBST falling threshold VBSTF 6.25 7.15 V VBSTR = VBST - VSH, -40°C to 125°C 5
GVDD quiescent current IGVDD 430 μA VINL = VINH = 0 V 5
GVDD operating current IDDO 0.56 mA f = 50 kHz, CLOAD = 0 5
Total BST quiescent current IBST 150 uA VINL = VINH = 0 V, VDD = 12 V 5
Total BST operating current IBSTO 0.16 mA f = 50 kHz, CLOAD = 0 5
BST to GND quiescent current IBSTS 33.3 μA VSH = VBST = 95 V, GVDD = 12 V 5
BST to GND operating current IBSTSO 0.07 mA f = 50 kHz, CLOAD = 0 5
Input voltage hysteresis VIHYS 0.15 V 5
Input pulldown resistance RIN 200 kΩ VIN = 3 V 5
GVDD threshold hysteresis VDDHYS 0.45 V 5
VBST threshold hysteresis VBSTHYS 0.45 V 5
GL low level output voltage VGL_L 0.25 V IGL = 100 mA, VGL_L = VGL, GND 5
GL high level output voltage VGL_H 0.8 V IGL = -100 mA, VGL_H = VGVDD, VGL 5
GL peak pullup current 0.5 A VGL = 0V 5
GL peak pulldown current 0.8 A VGL = 12V 5
GH low level output voltage VGH_L 0.25 V IGH = 100 mA, VGH_L = VGH, VSH 5
GH high level output voltage VGH_H 0.8 V IGH = -100 mA, VGH_H = VBST, VGH 5
GH peak pullup current 0.5 A VGH = 0V 5
GH peak pulldown current 0.8 A VGH = 12V 5
VINL falling to VGL falling tDLFF 115 ns VINH = VINL = 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 90% of the output. 5
VINH falling to VGH falling tDHFF 115 ns VINH = VIN L= 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 90% of the output. 6
VINL rising to VGL rising tDLRR 115 ns VINH = VINL = 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 10% of the output. 6
VINH rising to VGH rising tDHRR 115 ns VINH = VINL = 0-3 V, CLOAD = 0 pF. Time from 50% of the input to 10% of the output. 6
Delay from GL on to GH off tMON 30 ns INL ON, INH OFF, VINH = VINL = 0-3 V 6
Delay from GL off to GH on tMOFF 30 ns INL OFF, INH ON, VINH = VINL = 0-3 V 6
GL rise time tR_GL 28 ns CLOAD = 1000 pF, VINH = VINL = 0-3 V 6
GH rise time tR_GH 28 ns CLOAD = 1000 pF, VINH = VINL = 0-3 V 6
GL fall time tF_GL 18 ns CLOAD = 1000 pF, VINH = VINL = 0-3 V 6
GH fall time tF_GH 18 ns CLOAD = 1000 pF, VINH = VINL = 0-3 V 6
Junction-to-ambient thermal resistance RθJA 133.2 °C/W D (SOIC) 8 pins 4
Junction-to-case (top) thermal resistance RθJC(top) 75.2 °C/W D (SOIC) 8 pins 4
Junction-to-board thermal resistance RθJB 76.7 °C/W D (SOIC) 8 pins 4
Junction-to-top characterization parameter ψJT 25.5 °C/W D (SOIC) 8 pins 4
Junction-to-board characterization parameter ψJB 75.9 °C/W D (SOIC) 8 pins 4

CAD (KiCad official)

  • Symbol: LM2101DR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOIC-8 (KiCad packages3D, STEP)
  • 3D model files: lm2101dr-etched.step / lm2101dr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lm2101dr.step / lm2101dr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (32 pp, sha256 a8486ca40001093e, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF