component
LM20333MH
Public Made by Adomby adom
Texas Instruments DC-DC Converters, HTSSOP-20-EP. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LM20333MH
Texas Instruments · DC-DC Converters · HTSSOP-20-EP
LM20333MH from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SS/TRK | input | Soft-start or tracking control input; an internal 4.5 µA source charges an external capacitor to set the soft-start rate, and if left open an internal 1 ms SS ramp is activated. |
| 2 | FB | input | Feedback input to the inverting input of the internal transconductance error amplifier, referenced to an internal 800 mV reference. |
| 3 | PGOOD | output | Open-drain power good output indicating the output voltage is regulating within tolerance; a 10 kΩ to 100 kΩ pull-up resistor is recommended if used. |
| 4 | COMP | passive | Output of the internal error amplifier and input to the PWM; the loop compensation network connects between COMP and AGND. |
| 5 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 6 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 7 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 8 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 9 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 10 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 11 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 12 | AGND | power_in | Analog ground, the internal reference for the regulator control functions. |
| 13 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 14 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 15 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 16 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 17 | BOOT | passive | Bootstrap input; an internal diode from VCC to BOOT charges the external capacitor required from SW to BOOT to power the control MOSFET gate driver. |
| 18 | VCC | power_out | Output of the high-voltage linear regulator that tracks VIN up to about 7.2 V and is regulated to approximately 5.5 V; requires a 0.1 µF to 1 µF ceramic decoupling capacitor and is output only. |
| 19 | EN | input | Enable or UVLO input; an external voltage divider sets the line undervoltage lockout threshold, and an internal 2 µA pull-up enables the regulator if the pin is left unconnected. |
| 20 | SYNC | input | Frequency synchronization input; an external clock sets the switching frequency, which can be synchronized from 250 kHz to 1.5 MHz, and the device operates at approximately 200 kHz if left open. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management ICs |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND (operating range) | 4.5 | 36 | V | 3 | |||
| Junction Temperature (operating) | -40 | 125 | °C | 3 | |||
| VIN to GND | -0.3 | 38 | V | 3 | |||
| BOOT to GND | -0.3 | 43 | V | 3 | |||
| BOOT to SW | -0.3 | 7 | V | 3 | |||
| SW to GND | -0.5 | 38 | V | 3 | |||
| SW to GND (Transient) | -1.5 | V | < 20 ns | 3 | |||
| FB, EN, SS/TRK, COMP, SYNC, PGOOD to GND | -0.3 | 6 | V | 3 | |||
| VCC to GND | -0.3 | 8 | V | 3 | |||
| Storage Temperature | -65 | 150 | °C | 3 | |||
| Feedback Pin Voltage | VFB | 0.788 | 0.8 | 0.812 | V | VVIN = 4.5V to 36V | 3 |
| High-Side MOSFET On-Resistance | RHSW-DS(ON) | 130 | 225 | mΩ | ISW = 3A | 3 | |
| Low-Side MOSFET On-Resistance | RLSW-DS(ON) | 110 | 190 | mΩ | ISW = 3A | 3 | |
| Operating Quiescent Current | IQ | 2.3 | 3 | mA | VVIN = 4.5V to 36V | 3 | |
| Shutdown Quiescent Current | ISD | 150 | 180 | µA | VEN = 0V | 3 | |
| VIN Under Voltage Lockout Rising | VUVLO | 4 | 4.25 | 4.5 | V | VVIN | 3 |
| VIN Under Voltage Lockout Hysteresis | VUVLO(HYS) | 350 | 450 | mV | 3 | ||
| Soft-Start Pin Source Current | ISS | 2 | 4.5 | 7 | µA | VSS = 0V | 3 |
| Soft-Start/Track Pin Accuracy | VTRKACC | -10 | 5 | 15 | mV | VSS = 0.4V | 3 |
| BOOT Diode Forward Voltage | VF-BOOT | 0.9 | 1.1 | V | IBOOT = -100 mA | 3 | |
| Over Voltage Protection Rising Threshold | VFB(OVP) | 107 | 110 | 112 | % | 3 | |
| Over Voltage Protection Hysteresis | VFB(OVP-HYS) | 2 | 3 | % | 3 | ||
| PGOOD Threshold, VOUT Rising | VFB(PG) | 93 | 95 | 97 | % | 3 | |
| PGOOD Hysteresis | VFB(PG-HYS) | 2 | 3 | % | 3 | ||
| PGOOD Low Sink Current | IPGOOD(SNK) | 0.6 | 1 | mA | VPGOOD = 0.5V | 3 | |
| PGOOD High Leakage Current | IPGOOD(SRC) | 5 | 200 | nA | VPGOOD = 5V | 3 | |
| Oscillator Frequency | FOSC | 160 | 200 | 240 | kHz | VSYNC = 0V | 3 |
| Maximum SYNC Frequency | FOSCH | 1500 | kHz | 3 | |||
| Minimum SYNC Frequency | FOSCL | 250 | kHz | 4 | |||
| SYNC pin Logic High | VIH_SYNC | 2 | V | 4 | |||
| SYNC pin Logic Low | VIL_SYNC | 0.8 | V | 4 | |||
| COMP Output Source Current | ICOMP(SRC) | 200 | 400 | µA | VFB = 0V, VCOMP = 0V | 4 | |
| COMP Output Sink Current | ICOMP(SNK) | 200 | 350 | µA | VFB = 1.6V, VCOMP = 1.6V | 4 | |
| Error Amplifier DC Transconductance | gm | 450 | 515 | 600 | µmho | ICOMP = -50 µA to +50 µA | 4 |
| Cycle By Cycle Positive Current Limit | ILIM | 4.3 | 5.2 | 6 | A | 4 | |
| EN Pin Rising Threshold | VEN(RISING) | 1.2 | 1.25 | 1.3 | V | 4 | |
| VCC Voltage | VVCC | 5.5 | V | IVCC = -5 mA, VEN = 5V | 3 | ||
| IBOOT BOOT Diode Leakage | IBOOT | 10 | nA | VBOOT = 4V | 3 | ||
| PGOOD Delay | TPGOOD | 20 | µs | 3 | |||
| SYNC pin input leakage | ISYNC | 10 | nA | VSYNC = 5V | 4 | ||
| Minimum Off Time | TMIN | 170 | ns | ILOAD = 3A | 4 | ||
| Feedback Pin Bias Current | IFB | 50 | nA | VFB = 1V | 4 | ||
| Error Amplifier Voltage Gain | AVOL | 2000 | V/V | COMP pin open | 4 | ||
| Error Amplifier Gain-Bandwidth Product | GBW | 7 | MHz | COMP pin open | 4 | ||
| Cycle By Cycle Negative Current Limit | ILIMNEG | 2.8 | A | 4 | |||
| Cycle By Cycle Current Limit Delay | TILIM | 150 | ns | 4 | |||
| EN Pin Hysteresis | VEN(HYS) | 50 | mV | 4 | |||
| EN Source Current | IEN | 2 | µA | VEN = 0V, VVIN = 12V | 4 | ||
| Thermal Shutdown | TSD | 170 | °C | 4 | |||
| Thermal Shutdown Hysteresis | TSD(HYS) | 20 | °C | 4 | |||
| Junction to Case thermal resistance | θJC | 5.6 | °C/W | 4 | |||
| Junction to Ambient thermal resistance | θJA | 27 | °C/W | 0 LFM airflow | 4 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | Human Body Model(3) 2kV (1) Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for | 3 | |
| contacts | copper | pad (EP). The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. Since the LM20333 has the SW pins on opposite sides of | 21 |
CAD (KiCad official)
- Symbol:
LM20333MH - Footprint:
Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm - 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
lm20333mh-etched.step/lm20333mh-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm20333mh.step/lm20333mh.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Texas Instruments datasheet (31 pp, sha256
9b3881a6f858d693, retrieved 2026-10-30, tier: manufacturer) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LM20333MH
**Texas Instruments** · DC-DC Converters · HTSSOP-20-EP
LM20333MH from Texas Instruments, in a HTSSOP-20-EP. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | SS/TRK | input | Soft-start or tracking control input; an internal 4.5 µA source charges an external capacitor to set the soft-start rate, and if left open an internal 1 ms SS ramp is activated. |
| 2 | FB | input | Feedback input to the inverting input of the internal transconductance error amplifier, referenced to an internal 800 mV reference. |
| 3 | PGOOD | output | Open-drain power good output indicating the output voltage is regulating within tolerance; a 10 kΩ to 100 kΩ pull-up resistor is recommended if used. |
| 4 | COMP | passive | Output of the internal error amplifier and input to the PWM; the loop compensation network connects between COMP and AGND. |
| 5 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 6 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 7 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 8 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 9 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 10 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 11 | GND | power_in | Ground, the internal reference for the power MOSFETs. |
| 12 | AGND | power_in | Analog ground, the internal reference for the regulator control functions. |
| 13 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 14 | SW | output | Switch node; the drain of the internal synchronous rectifier power NMOSFET and the source of the internal control power NMOSFET. |
| 15 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 16 | VIN | power_in | Input supply voltage with a nominal operating range of 4.5 V to 36 V. |
| 17 | BOOT | passive | Bootstrap input; an internal diode from VCC to BOOT charges the external capacitor required from SW to BOOT to power the control MOSFET gate driver. |
| 18 | VCC | power_out | Output of the high-voltage linear regulator that tracks VIN up to about 7.2 V and is regulated to approximately 5.5 V; requires a 0.1 µF to 1 µF ceramic decoupling capacitor and is output only. |
| 19 | EN | input | Enable or UVLO input; an external voltage divider sets the line undervoltage lockout threshold, and an internal 2 µA pull-up enables the regulator if the pin is left unconnected. |
| 20 | SYNC | input | Frequency synchronization input; an external clock sets the switching frequency, which can be synchronized from 250 kHz to 1.5 MHz, and the device operates at approximately 200 kHz if left open. |
| 21 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Texas Instruments |
| Package | HTSSOP-20-EP |
| Category | Power Management ICs |
| Pins | 21 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND (operating range) | | 4.5 | | 36 | V | | 3 |
| Junction Temperature (operating) | | -40 | | 125 | °C | | 3 |
| VIN to GND | | -0.3 | | 38 | V | | 3 |
| BOOT to GND | | -0.3 | | 43 | V | | 3 |
| BOOT to SW | | -0.3 | | 7 | V | | 3 |
| SW to GND | | -0.5 | | 38 | V | | 3 |
| SW to GND (Transient) | | -1.5 | | | V | < 20 ns | 3 |
| FB, EN, SS/TRK, COMP, SYNC, PGOOD to GND | | -0.3 | | 6 | V | | 3 |
| VCC to GND | | -0.3 | | 8 | V | | 3 |
| Storage Temperature | | -65 | | 150 | °C | | 3 |
| Feedback Pin Voltage | VFB | 0.788 | 0.8 | 0.812 | V | VVIN = 4.5V to 36V | 3 |
| High-Side MOSFET On-Resistance | RHSW-DS(ON) | | 130 | 225 | mΩ | ISW = 3A | 3 |
| Low-Side MOSFET On-Resistance | RLSW-DS(ON) | | 110 | 190 | mΩ | ISW = 3A | 3 |
| Operating Quiescent Current | IQ | | 2.3 | 3 | mA | VVIN = 4.5V to 36V | 3 |
| Shutdown Quiescent Current | ISD | | 150 | 180 | µA | VEN = 0V | 3 |
| VIN Under Voltage Lockout Rising | VUVLO | 4 | 4.25 | 4.5 | V | VVIN | 3 |
| VIN Under Voltage Lockout Hysteresis | VUVLO(HYS) | | 350 | 450 | mV | | 3 |
| Soft-Start Pin Source Current | ISS | 2 | 4.5 | 7 | µA | VSS = 0V | 3 |
| Soft-Start/Track Pin Accuracy | VTRKACC | -10 | 5 | 15 | mV | VSS = 0.4V | 3 |
| BOOT Diode Forward Voltage | VF-BOOT | | 0.9 | 1.1 | V | IBOOT = -100 mA | 3 |
| Over Voltage Protection Rising Threshold | VFB(OVP) | 107 | 110 | 112 | % | | 3 |
| Over Voltage Protection Hysteresis | VFB(OVP-HYS) | | 2 | 3 | % | | 3 |
| PGOOD Threshold, VOUT Rising | VFB(PG) | 93 | 95 | 97 | % | | 3 |
| PGOOD Hysteresis | VFB(PG-HYS) | | 2 | 3 | % | | 3 |
| PGOOD Low Sink Current | IPGOOD(SNK) | | 0.6 | 1 | mA | VPGOOD = 0.5V | 3 |
| PGOOD High Leakage Current | IPGOOD(SRC) | | 5 | 200 | nA | VPGOOD = 5V | 3 |
| Oscillator Frequency | FOSC | 160 | 200 | 240 | kHz | VSYNC = 0V | 3 |
| Maximum SYNC Frequency | FOSCH | | | 1500 | kHz | | 3 |
| Minimum SYNC Frequency | FOSCL | 250 | | | kHz | | 4 |
| SYNC pin Logic High | VIH_SYNC | 2 | | | V | | 4 |
| SYNC pin Logic Low | VIL_SYNC | | | 0.8 | V | | 4 |
| COMP Output Source Current | ICOMP(SRC) | | 200 | 400 | µA | VFB = 0V, VCOMP = 0V | 4 |
| COMP Output Sink Current | ICOMP(SNK) | | 200 | 350 | µA | VFB = 1.6V, VCOMP = 1.6V | 4 |
| Error Amplifier DC Transconductance | gm | 450 | 515 | 600 | µmho | ICOMP = -50 µA to +50 µA | 4 |
| Cycle By Cycle Positive Current Limit | ILIM | 4.3 | 5.2 | 6 | A | | 4 |
| EN Pin Rising Threshold | VEN(RISING) | 1.2 | 1.25 | 1.3 | V | | 4 |
| VCC Voltage | VVCC | | 5.5 | | V | IVCC = -5 mA, VEN = 5V | 3 |
| IBOOT BOOT Diode Leakage | IBOOT | | 10 | | nA | VBOOT = 4V | 3 |
| PGOOD Delay | TPGOOD | | 20 | | µs | | 3 |
| SYNC pin input leakage | ISYNC | | 10 | | nA | VSYNC = 5V | 4 |
| Minimum Off Time | TMIN | | 170 | | ns | ILOAD = 3A | 4 |
| Feedback Pin Bias Current | IFB | | 50 | | nA | VFB = 1V | 4 |
| Error Amplifier Voltage Gain | AVOL | | 2000 | | V/V | COMP pin open | 4 |
| Error Amplifier Gain-Bandwidth Product | GBW | | 7 | | MHz | COMP pin open | 4 |
| Cycle By Cycle Negative Current Limit | ILIMNEG | | 2.8 | | A | | 4 |
| Cycle By Cycle Current Limit Delay | TILIM | | 150 | | ns | | 4 |
| EN Pin Hysteresis | VEN(HYS) | | 50 | | mV | | 4 |
| EN Source Current | IEN | | 2 | | µA | VEN = 0V, VVIN = 12V | 4 |
| Thermal Shutdown | TSD | | 170 | | °C | | 4 |
| Thermal Shutdown Hysteresis | TSD(HYS) | | 20 | | °C | | 4 |
| Junction to Case thermal resistance | θJC | | 5.6 | | °C/W | | 4 |
| Junction to Ambient thermal resistance | θJA | | 27 | | °C/W | 0 LFM airflow | 4 |
## Materials and finish
As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| housing | Abs | | Human Body Model(3) 2kV (1) Absolute Maximum Ratings indicate limits beyond witch damage to the device may occur. Operating Ratings indicate conditions for | 3 |
| contacts | copper | | pad (EP). The inductor should be placed as close as possible to the SW pin and output capacitor. 2. Minimize the copper area of the switch node. Since the LM20333 has the SW pins on opposite sides of | 21 |
## CAD (KiCad official)
- Symbol: `LM20333MH`
- Footprint: `Package_SO:TSSOP-20-1EP_4.4x6.5mm_P0.65mm_EP2.15x3.35mm`
- 3D model: HTSSOP-20-EP, generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 1.2 mm nominal TSSOP height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `lm20333mh-etched.step` / `lm20333mh-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lm20333mh.step` / `lm20333mh.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Texas Instruments datasheet](https://www.ti.com/lit/ds/symlink/lm20333mh.pdf) (31 pp, sha256 `9b3881a6f858d693`, retrieved 2026-10-30, tier: manufacturer)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lm20333mh-datasheet.pdf)