component
LM-STL45N10F7AG
Public Made by Adomby adom
Leiditech MOSFETs, DFN5x6-8L. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Made with KiCad 10.0 · needs KiCad 10.0 or later to open · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 12d ago |
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| lm-stl45n10f7ag-etched.glb | 12d ago |
| lm-stl45n10f7ag-etched.step | 12d ago |
| lm-stl45n10f7ag-hero.glb | 12d ago |
| lm-stl45n10f7ag-hero.overlay.json | 12d ago |
| lm-stl45n10f7ag.glb | 12d ago |
| lm-stl45n10f7ag.kicad_mod | 12d ago |
| lm-stl45n10f7ag.kicad_sym | 12d ago |
| lm-stl45n10f7ag.lbr | 12d ago |
| lm-stl45n10f7ag.step | 12d ago |
| package.json | 12d ago |
| page.json | 12d ago |
| README.md | 12d ago |
LM-STL45N10F7AG
Leiditech · MOSFETs · DFN5x6-8L
LM-STL45N10F7AG from Leiditech, in a DFN5x6-8L. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | S | passive | Source terminal of the N-channel MOSFET (pin 1, marked by the dot/Pin1 arrow); VDS rating 100 V, continuous drain current 40 A. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, shorted to the other source pins; carries up to 40 A continuous drain current. |
| 3 | S | passive | Source terminal of the N-channel MOSFET, shorted to the other source pins; carries up to 40 A continuous drain current. |
| 4 | G | input | Gate terminal of the MOSFET; gate-source voltage limited to ±20 V, with a gate threshold of 1.0 to 2.5 V. |
| 5 | D | passive | Drain terminal of the MOSFET; drain-source voltage rated 100 V, pulsed drain current 120 A. |
| 6 | D | passive | Drain terminal of the MOSFET, shorted to the other drain pins; drain-source voltage rated 100 V. |
| 7 | D | passive | Drain terminal of the MOSFET, shorted to the other drain pins; drain-source voltage rated 100 V. |
| 8 | D | passive | Drain terminal of the MOSFET, shorted to the other drain pins; drain-source voltage rated 100 V. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | DFN5x6-8L |
| Category | Transistors/Thyristors |
| Pins | 9 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain source voltage | VDS | 100 | V | 1 | |||
| Gate source voltage | VGS | -20 | 20 | V | 1 | ||
| Continuous drain current | ID | 40 | A | TC=25 ℃ | 1 | ||
| Pulsed drain current | ID, pulse | 120 | A | TC=25 ℃ | 1 | ||
| Power dissipation | PD | 72 | W | TC=25 ℃ | 1 | ||
| Single pulsed avalanche energy | EAS | 30 | mJ | 1 | |||
| Operation and storage temperature | Tstg, Tj | -55 | 150 | ℃ | 1 | ||
| Drain-source breakdown voltage | BVDSS | 100 | V | VGS=0 V, ID=250 μA | 2 | ||
| Gate threshold voltage | VGS(th) | 1 | 2.5 | V | VDS=VGS, ID=250 μA | 2 | |
| Drain-source on-state resistance | RDS(ON) | 16 | 20 | mΩ | VGS=10 V, ID=8 A | 2 | |
| Drain-source on-state resistance | RDS(ON) | 26 | mΩ | VGS=4.5 V, ID=6 A | 2 | ||
| Gate-source leakage current | IGSS | 100 | nA | VGS=20 V | 2 | ||
| Gate-source leakage current | IGSS | -100 | nA | VGS=20 V | 2 | ||
| Drain-source leakage current | IDSS | 1 | μA | VDS=100 V, VGS=0 V | 2 | ||
| Diode forward current | IS | 40 | A | VGS<Vth | 2 | ||
| Pulsed source current | ISP | 120 | A | 2 | |||
| Input capacitance | Ciss | 1190.6 | pF | VGS=0 V, VDS=50 V, ƒ=1 MHz | 2 | ||
| Output capacitance | Coss | 194.6 | pF | VGS=0 V, VDS=50 V, ƒ=1 MHz | 2 | ||
| Reverse transfer capacitance | Crss | 4.1 | pF | VGS=0 V, VDS=50 V, ƒ=1 MHz | 2 | ||
| Turn-on delay time | td(on) | 17.8 | ns | VGS=10 V, VDS=50 V, RG=2.2 Ω, ID=10 A | 2 | ||
| Rise time | tr | 3.9 | ns | VGS=10 V, VDS=50 V, RG=2.2 Ω, ID=10 A | 2 | ||
| Turn-off delay time | td(off) | 33.5 | ns | VGS=10 V, VDS=50 V, RG=2.2 Ω, ID=10 A | 2 | ||
| Fall time | tf | 3.2 | ns | VGS=10 V, VDS=50 V, RG=2.2 Ω, ID=10 A | 2 | ||
| Total gate charge | Qg | 19.8 | nC | ID=8 A, VDS=50 V, VGS=10 V | 2 | ||
| Gate-source charge | Qgs | 2.4 | nC | ID=8 A, VDS=50 V, VGS=10 V | 2 | ||
| Gate-drain charge | Qgd | 5.3 | nC | ID=8 A, VDS=50 V, VGS=10 V | 2 | ||
| Gate plateau voltage | Vplateau | 3.2 | V | 2 | |||
| Diode forward voltage | VSD | 1.3 | V | IS=8 A, VGS=0 V | 2 | ||
| Reverse recovery time | trr | 50.2 | ns | IS=8 A, di/dt=100 A/μs | 2 | ||
| Reverse recovery charge | Qrr | 95.1 | nC | IS=8 A, di/dt=100 A/μs | 2 | ||
| Peak reverse recovery current | Irrm | 2.5 | A | IS=8 A, di/dt=100 A/μs | 2 | ||
| Thermal resistance, junction-case | RθJC | 1.74 | ℃/W | 1 | |||
| Thermal resistance, junction-ambient | RθJA | 62 | ℃/W | 1 |
CAD (KiCad official)
- Symbol:
LM-STL45N10F7AG - Footprint:
Package_DFN_QFN:DFN-S-8-1EP_6x5mm_P1.27mm - 3D model: DFN5x6-8L (KiCad packages3D, STEP)
- 3D model files:
lm-stl45n10f7ag-etched.step/lm-stl45n10f7ag-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm-stl45n10f7ag.step/lm-stl45n10f7ag.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leiditech datasheet (6 pp, sha256
95cb43363d80b188, retrieved 2026-10-21, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).