component
LM-PESD5V0V4UW
Public Made by Adomby adom
Leiditech ESD And Surge Protection (TVS/ESD), SOT-553. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM-PESD5V0V4UW
Leiditech · ESD And Surge Protection (TVS/ESD) · SOT-553
LM-PESD5V0V4UW from Leiditech, in a SOT-553. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | I/O1 | passive | TVS diode array channel connected to the common internal node (pin 2); protects to ±15kV air / ±8kV contact per IEC 61000-4-2 with VRWM 5V. |
| 2 | GND | power_in | Common internal node of the TVS diode array, shown tied to the diode junctions in the pin configuration diagram. |
| 3 | I/O3 | passive | TVS diode array channel connected to the common internal node (pin 2); protects to ±15kV air / ±8kV contact per IEC 61000-4-2 with VRWM 5V. |
| 4 | I/O4 | passive | TVS diode array channel connected to the common internal node (pin 2); protects to ±15kV air / ±8kV contact per IEC 61000-4-2 with VRWM 5V. |
| 5 | I/O5 | passive | TVS diode array channel connected to the common internal node (pin 2); protects to ±15kV air / ±8kV contact per IEC 61000-4-2 with VRWM 5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | SOT-553 |
| Category | Circuit Protection |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Reverse working voltage | VRWM | 5 | V | TA=25°C | 2 | ||
| Breakdown voltage | VBR | 6 | V | IT=1mA | 2 | ||
| Clamping voltage | VC | 9.8 | V | @1A | 2 | ||
| Clamping voltage | VC | 12 | V | @5A | 2 | ||
| Reverse leakage current | IR | 0.5 | µA | 2 | |||
| Capacitance | C | 0.7 | pF | 2 | |||
| Peak Pulse Power | Ppp | 60 | W | 8/20µs, Tamb=25°C | 1 | ||
| ESD per IEC 61000-4-2 (Air) | VESD | -15 | 15 | kV | Tamb=25°C | 1 | |
| ESD per IEC 61000-4-2 (Contact) | VESD | -8 | 8 | kV | Tamb=25°C | 1 | |
| Operating Temperature Range | TJ | -55 | 125 | °C | 1 | ||
| Storage Temperature Range | TSTJ | -55 | 150 | °C | 1 |
CAD (KiCad official)
- Symbol:
LM-PESD5V0V4UW - Footprint:
Package_TO_SOT_SMD:SOT-553 - 3D model: SOT-553 (KiCad packages3D, STEP)
- 3D model files:
lm-pesd5v0v4uw-etched.step/lm-pesd5v0v4uw-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm-pesd5v0v4uw.step/lm-pesd5v0v4uw.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leiditech datasheet (3 pp, sha256
156418ad47cc442d, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).