component
LM-2N7002LT1G
Public Made by Adomby adom
Leiditech MOSFETs, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownLM-2N7002LT1G
Leiditech · MOSFETs · SOT-23
LM-2N7002LT1G from Leiditech, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | G | input | Gate, voltage-controlled input with VGS limit of ±20 V and threshold VGS(th) of 1 V min to 2.5 V max at ID=250 µA. |
| 2 | S | passive | Source terminal of the N-channel MOSFET, with body-diode continuous current IS of 340 mA max. |
| 3 | D | passive | Drain terminal, rated for VDS of 60 V and continuous drain current ID of 340 mA at TA=25℃ (1.5 A pulsed). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Leiditech |
| Package | SOT-23 |
| Category | Transistors/Thyristors |
| Pins | 3 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Drain-Source Breakdown Voltage | BVDSS | 60 | V | VGS= 0V, ID=250μA | 2 | ||
| Zero Gate Voltage Drain Current | IDSS | 1 | μA | VDS=60V,VGS=0V | 2 | ||
| Gate-Body Leakage Current | IGSS1 | -100 | 100 | nA | VGS= ±20V, VDS=0V | 2 | |
| Gate-Body Leakage Current | IGSS2 | -50 | 50 | nA | VGS= ±10V, VDS=0V | 2 | |
| Gate Threshold Voltage | VGS(th) | 1 | 1.5 | 2.5 | V | VDS= VGS, ID=250μA | 2 |
| Static Drain-Source On-Resistance | RDS(ON) | 1.2 | 2.5 | Ω | VGS= 10V, ID=-300mA | 2 | |
| Static Drain-Source On-Resistance | RDS(ON) | 1.3 | 3 | Ω | VGS= 4.5V, ID=200mA | 2 | |
| Diode Forward Voltage | VSD | 1.2 | V | IS=300mA,VGS=0V | 2 | ||
| Maximum Body-Diode Continuous Current | IS | 340 | mA | 2 | |||
| Total Gate Charge | Qg | 1.7 | 2.4 | nC | VGS=10V,VDS=30V,ID=0.3A | 2 | |
| Reverse recovery Time | trr | 30 | ns | VGS=0V,IS=300mA,VR=25V, dIS/dt=-100A/μs | 2 | ||
| Input Capacitance | Ciss | 16 | pF | VDS=30V,VGS=0V,f=1MHZ | 2 | ||
| Output Capacitance | Coss | 10 | pF | VDS=30V,VGS=0V,f=1MHZ | 2 | ||
| Reverse Transfer Capacitance | Crss | 5.5 | pF | VDS=30V,VGS=0V,f=1MHZ | 2 | ||
| Turn-on Delay Time | tD(on) | 5 | ns | VGS=10V,VDD=30V, ID=300mA, RGEN=6Ω | 2 | ||
| Turn-off Delay Time | tD(off) | 17 | ns | VGS=10V,VDD=30V, ID=300mA, RGEN=6Ω | 2 | ||
| Drain-source Voltage | VDS | 60 | V | TA=25℃ | 1 | ||
| Gate-source Voltage | VGS | -20 | 20 | V | TA=25℃ | 1 | |
| Drain Current | ID | 340 | mA | TA=25℃ @ Steady State | 1 | ||
| Drain Current | ID | 272 | mA | TA=70℃ @ Steady State | 1 | ||
| Pulsed Drain Current | IDM | 1.5 | A | TA=25℃ | 1 | ||
| Total Power Dissipation | PD | 350 | mW | TA=25℃ | 1 | ||
| Junction and Storage Temperature Range | TJ,TSTG | -55 | 150 | ℃ | 1 | ||
| Thermal Resistance Junction-to-Ambient | RθJA | 357 | ℃/W | Steady State, FR-4 PCB 1 inch x 0.85 inch x 0.062 inch | 1 |
CAD (KiCad official)
- Symbol:
LM-2N7002LT1G - Footprint:
Package_TO_SOT_SMD:SOT-23 - 3D model: SOT-23 (KiCad packages3D, STEP)
- 3D model files:
lm-2n7002lt1g-etched.step/lm-2n7002lt1g-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lm-2n7002lt1g.step/lm-2n7002lt1g.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Leiditech datasheet (5 pp, sha256
f03f57dfcf4c93bd, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).