component

LKS561

Public Made by Adom

by adom

LINKOSEMI Gate Drive ICs, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icslks561factory-2.0.0extractor-text

Verified LKS561

by Ray · last 6 Nov 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

6 Nov 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: LKS561 · SOP-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 13-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-szu8yay2/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓symbol_text: no pin names collide
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ lks561.kicad_sym✓ lks561.kicad_mod✓ lks561.step
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Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 1d ago
viewers lks561: viewers · Ray 1d ago
lks561-etched.glb Publish 0.1.0 · Ray 1d ago
lks561-etched.step lks561: factory component page (tier=lcsc) · Ray 1d ago
lks561-hero.glb lks561: hero GLB from the etched model (keeps the MPN mark) · Ray 1d ago
lks561-hero.overlay.json Publish 0.1.0 · Ray 1d ago
lks561.glb Publish 0.1.0 · Ray 1d ago
lks561.kicad_mod Publish 0.1.0 · Ray 1d ago
lks561.kicad_sym Publish 0.1.0 · Ray 1d ago
lks561.lbr Publish 0.1.0 · Ray 1d ago
lks561.step Publish 0.1.0 · Ray 1d ago
package.json Publish 0.1.0 · Ray 1d ago
page.json Set visibility: public · Ray 1d ago
README.md Publish 0.1.0 · Ray 1d ago
verification.json Verified: Published by the parts factory: tier lcsc, 8 pins · Ray 1d ago

LKS561

LINKOSEMI · Gate Drive ICs · SOP-8

LKS561 from LINKOSEMI, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VCC power_in Chip supply voltage, recommended 10 to 25 V, with an absolute maximum of 35 V (-0.3 V to 35 V).
2 HIN input High-side input signal where logic '1' turns the high-side output on; VIH minimum is 3 V, VIL maximum is 0.8 V, and the input range is 0 to VCC.
3 LIN input Low-side input signal where logic '1' turns the low-side output on; VIH minimum is 3 V, VIL maximum is 0.8 V, and the input range is 0 to VCC.
4 COM power_in Chip ground reference for the device.
5 LO output Low-side gate drive output, rated at a drive current of ±1.2 A/1.5 A and swinging between 0 V and VCC.
6 VS power_in High-side floating offset voltage, recommended -10.8 V to 150 V, with dVS/dt limited to 55 V/ns and VS kept between VB-25 V and VB+0.3 V.
7 HO output High-side gate drive output referenced to VS, swinging between VS and VB.
8 VB power_in High-side floating supply voltage, recommended VS+10 V to VS+20 V, with an absolute maximum of 300 V.

Key specifications

Parameter Value
Manufacturer LINKOSEMI
Package SOP-8
Category Power Management ICs
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
高侧浮动输入电源电压 (VB) absolute maximum VB -0.3 300 V 10
芯片供电电压 (VCC) absolute maximum VCC -0.3 35 V 10
高侧浮动偏置电压变化率 dVS/dt dVS/dt 55 V/ns 10
功率耗散 PD PD 0.625 W TA +25°C, SOIC-8 10
结对环境热阻 RthJA RthJA 200 °C/W SOIC-8 10
结温 TJ TJ -40 150 °C 10
储存温度 TS TS -55 175 °C 10
引脚温度 TL TL 300 10 s soldering 10
高侧浮动偏置电压 (VS) recommended VS -10.8 150 V 10
芯片供电电压 (VCC) recommended VCC 10 25 V 10
工作温度 TA TA -40 150 °C 10
导通延时 ton ton 600 700 ns VS = 0V 11
关断延时 toff toff 280 400 ns VS = 90V 11
导通上升沿 tr tr 600 750 ns 11
关断下降沿 tf tf 190 300 ns 11
死区时间 DT DT 180 200 260 ns 11
延时匹配度 MT MT 60 ns 11
欠压保护电压上阈值 VCCUV+ VCCUV+ 6.1 7.1 8.1 V 12
欠压保护电压下阈值 VCCUV- VCCUV- 5.8 6.8 7.8 V 12
VCC静态电流 IQCC IQCC 300 500 uA Vin=0/5V 12
VBS静态电流 IQBS IQBS 100 200 uA Vin=0/5V 12
高侧偏置电源漏电流 ILK ILK 50 uA VB=VS=90V 12
输入信号逻辑1的电压范围 VIH VIH 3 V VCC=10~20V 12
输入信号逻辑0的电压范围 VIL VIL 0.8 V VCC=10~20V 12
输入信号逻辑1的偏置电流 IIN+ IIN+ 3 10 uA VIN=5V, LIN=0V 12
输入信号逻辑0的偏置电流 IIN- IIN- 1 uA VIN=5V, LIN=0V 12
LO/HO输出高电压短路脉冲拉电流 IO+ IO+ 1000 1200 mA VO=0V, VIN=VIH, PW 10 us 12
LO/HO输出低电压短路脉冲灌电流 IO- IO- 1200 1500 mA VO=15V, VIN=VIL, PW 10 us 12

CAD (KiCad official)

  • Symbol: LKS561
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: lks561-etched.step / lks561-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lks561.step / lks561.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LINKOSEMI datasheet (13 pp, sha256 634d5c1d2e1909fb, retrieved 2026-11-06, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF