component
LKS32MC070RBT8
Public Made by Adomby adom
LINKOSEMI Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownLKS32MC070RBT8
LINKOSEMI · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)
LKS32MC070RBT8 from LINKOSEMI, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | P0_0 | bidirectional | GPIO port P0.0 with alternate functions including CLKO, MCPWM_BKIN0, UART0_RXD, SPI_DI, ADC01_CH4, DAC0_OUT and DAC1_OUT, with a 10kΩ pull-up that software can disable. |
| 2 | P0_1 | bidirectional | GPIO port P0.1 with alternate functions ADC01_CH6 and EXTI1 as listed in the datasheet. |
| 3 | P0_2 | bidirectional | Defaults to the RST_n reset input; the datasheet recommends a 10nF-100nF capacitor to GND and a 10k-20k pull-up between RSTN and AVDD (100nF if an external pull-up is present), and P0.2 can be switched to GPIO with its 10kΩ pull-up disabled. |
| 4 | GND | power_in | Chip ground; the datasheet strongly recommends tying multiple ground pins together on the PCB. |
| 5 | AVDD | power_in | Chip power supply with a specified supply range of 2.5 to 5.5 V. |
| 6 | P3_2 | bidirectional | GPIO port P3.2 with MCPWM channel 3 high-side output (MCPWM_CH3P) and CLUOUT2 alternate functions. |
| 7 | P3_4 | bidirectional | GPIO port P3.4 with MCPWM channel 3 low-side output (MCPWM_CH3N) as its listed alternate function. |
| 8 | P0_3 | bidirectional | GPIO port P0.3 with MCPWM channel 4 high-side output, I2C SCL, TIM2_CH0, ADC01_CH7 and EXTI3 alternate functions, with a software-disablable 10kΩ pull-up. |
| 9 | P0_4 | bidirectional | GPIO port P0.4 with MCPWM channel 4 low-side output, I2C SDA, TIM2_CH1 and ADC01_CH8 alternate functions, with a software-disablable 10kΩ pull-up. |
| 10 | P0_5 | bidirectional | GPIO port P0.5 with HALL_IN0, MCPWM channel 5 high-side output, QEP0 Z-phase input and ADC01_CH9 alternate functions. |
| 11 | P0_6 | bidirectional | GPIO port P0.6 with HALL_IN1, MCPWM channel 5 low-side output, UART1_RXD, I2C SCL, TIM1_CH0, CAN_RX, CMP2_IN negative input, FLT, EXTI4 and WK2, with a software-disablable 10kΩ pull-up. |
| 12 | P0_7 | bidirectional | GPIO port P0.7 with HALL_IN2, MCPWM_BKIN1, UART1_TXD, I2C SDA, TIM1_CH1, CAN_TX, CMP2_IP0 positive input and FLT, with a software-disablable 10kΩ pull-up. |
| 13 | P1_1 | bidirectional | GPIO port P1.1 with SPI chip select (SPI_CS) and EXTI5 alternate functions. |
| 14 | P2_11 | bidirectional | GPIO port P2.11 with MCPWM channel 1 high-side output, TIM2_CH0 and CMP2_IP1 comparator positive input alternate functions. |
| 15 | P2_12 | bidirectional | GPIO port P2.12 with MCPWM channel 1 low-side output, SPI_CS, TIM2_CH1, ADC_TRIGGER0 debug output, CLUOUT3 and EXTI6 alternate functions. |
| 16 | P0_8 | bidirectional | Port pin P0.8; the datasheet lists no alternate functions for this pin. |
| 17 | P0_9 | bidirectional | GPIO port P0.9 with I2C SCL, TIM2_CH0 alternate functions and a software-disablable 10kΩ pull-up. |
| 18 | P0_10 | bidirectional | GPIO port P0.10 with I2C SDA and TIM2_CH1 alternate functions. |
| 19 | P0_11 | bidirectional | GPIO port P0.11 with HALL_IN0, TIM3_CH0, ADC1_CH11, CMP0_IP1 positive input, FLT, EXTI7 and WK3 alternate functions. |
| 20 | P0_12 | bidirectional | GPIO port P0.12 with HALL_IN1, TIM3_CH1, CAN_RX, ADC1_CH12, CMP0_IP2 positive input and FLT alternate functions. |
| 21 | P0_13 | bidirectional | GPIO port P0.13 with HALL_IN2, QEP0_Z, CAN_TX, ADC1_CH13, CMP0_IP3 positive input and FLT alternate functions. |
| 22 | P0_14 | bidirectional | GPIO port P0.14 with CMP0_OUT, MCPWM_BKIN1, UART0_TXD, SPI_CLK, I2C SCL, TIM0_CH1, QEP1_Z, ADC0_CH10, CMP0_IP4, EXTI8 and WK4 alternate functions, with a software-disablable 10kΩ pull-up. |
| 23 | P0_15 | bidirectional | GPIO port P0.15 with CMP2_OUT, MCPWM_CH0P, UART0_RXD, SPI_DO, I2C SDA, TIM0_CH0, ADC_TRIGGER1, CMP0_IN negative input, FLT and EXTI9, with a software-disablable 10kΩ pull-up. |
| 24 | P1_0 | bidirectional | GPIO port P1.0 with MCPWM_CH0N, UART0_TXD, SPI_DI, TIM0_BKIN and EXTI10 alternate functions, with a software-disablable 10kΩ pull-up. |
| 25 | P3_6 | bidirectional | Port pin P3.6; the datasheet lists no alternate functions for this pin. |
| 26 | P1_2 | bidirectional | GPIO port P1.2 with TIM3_CH0 alternate function. |
| 27 | P1_3 | bidirectional | GPIO port P1.3 with TIM3_CH1 and ADC01_CH5 alternate functions and a software-disablable 10kΩ pull-up. |
| 28 | P3_5 | input | Positive (non-inverting) input of operational amplifier 0 (OPA0_IP). |
| 29 | P3_7 | input | Negative (inverting) input of operational amplifier 0 (OPA0_IN). |
| 30 | P2_7 | bidirectional | GPIO port P2.7 that can also carry the OPA output (OPAx_OUT) buffer, 1.5V LDO output (LDO15), reference voltage (REF), ADC0_CH11 and CLKO, with a software-disablable 10kΩ pull-up. |
| 31 | P3_0 | input | Positive (non-inverting) input of operational amplifier 1 (OPA1_IP). |
| 32 | P3_1 | input | Negative (inverting) input of operational amplifier 1 (OPA1_IN). |
| 33 | P2_8 | bidirectional | GPIO port P2.8 that doubles as the external crystal oscillator input (OSC_IN), with UART1_RXD, SPI_DO and TIM3_CH0 alternate functions and a software-disablable 10kΩ pull-up. |
| 34 | P3_9 | bidirectional | GPIO port P3.9 that doubles as the external crystal oscillator output (OSC_OUT), with UART1_TXD and TIM3_CH1 alternate functions and a software-disablable 10kΩ pull-up. |
| 35 | P3_13 | bidirectional | Port pin P3.13; the datasheet lists no alternate functions for this pin. |
| 36 | P1_12 | bidirectional | Port pin P1.12; the datasheet lists no alternate functions for this pin. |
| 37 | P1_13 | bidirectional | GPIO port P1.13 with MCPWM_CH5P, SPI_CLK and TIM0_CH0 alternate functions. |
| 38 | P1_14 | bidirectional | GPIO port P1.14 with MCPWM_CH5N, SPI_DO and TIM0_CH1 alternate functions. |
| 39 | P1_15 | bidirectional | GPIO port P1.15 with MCPWM_CH4P, SPI_DI and TIM2_CH0 alternate functions. |
| 40 | P2_0 | bidirectional | GPIO port P2.0 with MCPWM_CH4N, SPI_CS and TIM2_CH1 alternate functions. |
| 41 | P1_4 | bidirectional | GPIO port P1.4 with MCPWM_CH0P and QEP0_Z alternate functions. |
| 42 | P1_5 | bidirectional | GPIO port P1.5 with MCPWM_CH0N alternate function. |
| 43 | P1_6 | bidirectional | GPIO port P1.6 with MCPWM_CH1P alternate function. |
| 44 | P1_7 | bidirectional | GPIO port P1.7 with MCPWM_CH1N alternate function. |
| 45 | P1_8 | bidirectional | GPIO port P1.8 with MCPWM_CH2P alternate function. |
| 46 | P1_9 | bidirectional | GPIO port P1.9 with MCPWM_CH2N alternate function. |
| 47 | P1_10 | bidirectional | GPIO port P1.10 with MCPWM_CH3P, UART0_RXD, I2C SCL, TIM0_CH0, ADC_TRIGGER0, ADC0_CH13, EXTI12 alternate functions, with a software-disablable 10kΩ pull-up. |
| 48 | P1_11 | bidirectional | GPIO port P1.11 with MCPWM_CH3N, UART0_TXD, I2C SDA, TIM0_CH1, ADC_TRIGGER1, SIF and CLUOUT2 alternate functions, with a software-disablable 10kΩ pull-up. |
| 49 | P3_10 | bidirectional | GPIO port P3.10 with MCPWM_CH4P and operational amplifier 2 positive input (OPA2_IP) alternate functions. |
| 50 | P3_11 | bidirectional | GPIO port P3.11 with MCPWM_CH4N and operational amplifier 2 negative input (OPA2_IN) alternate functions. |
| 51 | P2_9 | bidirectional | GPIO port P2.9 with MCPWM_CH5P, SPI_DI, I2C SCL, ADC0_CH12 and CMP0_IP0 positive input alternate functions, with a software-disablable 10kΩ pull-up. |
| 52 | P2_10 | bidirectional | GPIO port P2.10 with MCPWM_CH5N, SPI_DO and I2C SDA alternate functions, with a software-disablable 10kΩ pull-up. |
| 53 | P3_14 | input | Negative (inverting) input of operational amplifier 3 (OPA3_IN). |
| 54 | P3_15 | input | Positive (non-inverting) input of operational amplifier 3 (OPA3_IP). |
| 55 | P2_1 | bidirectional | GPIO port P2.1 with SPI_CLK, ADC1_CH10 and CMP1_IP0 positive input alternate functions. |
| 56 | P3_12 | bidirectional | Port pin P3.12; the datasheet lists no alternate functions for this pin. |
| 57 | P2_2 | bidirectional | GPIO port P2.2 with QEP1_Z and CMP1_IN negative input alternate functions. |
| 58 | P2_3 | bidirectional | GPIO port P2.3 with CMP1_OUT, MCPWM_BKIN0, SPI_CS, TIM0_CH1, QEP0_Z, CLUOUT3, FLT and EXTI13 alternate functions. |
| 59 | P2_4 | bidirectional | GPIO port P2.4 with CMP0_OUT, HALL_IN0, MCPWM_CH2P, UART1_RXD, SPI_CLK, TIM1_CH0, TIM2_CH0, ADC_TRIGGER0, CAN_RX, CMP1_IP1, FLT, EXTI14 and WK5, with a software-disablable 10kΩ pull-up. |
| 60 | P2_5 | bidirectional | GPIO port P2.5 with CMP1_OUT, HALL_IN1, MCPWM_CH2N, UART1_TXD, SPI_DO, TIM1_CH1, TIM2_CH1, ADC_TRIGGER1, CAN_TX, CMP1_IP2 and FLT, with a software-disablable 10kΩ pull-up. |
| 61 | P2_6 | bidirectional | GPIO port P2.6 with CMP2_OUT, HALL_IN2, MCPWM_CH3P, TIM0_BKIN, TIM3_CH0, ADC_TRIGGER0, SIF, CLUOUT0, CMP1_IP3 and FLT, with a software-disablable 10kΩ pull-up. |
| 62 | P2_13 | bidirectional | GPIO port P2.13 with MCPWM_CH3N, UART0_TXD, SPI_DO, I2C SCL and TIM3_CH1 alternate functions, with a software-disablable 10kΩ pull-up. |
| 63 | P2_14 | bidirectional | GPIO port P2.14 that carries the SWD clock (SWCLK) with SPI_DI and I2C SCL alternate functions and a fixed-on 10kΩ pull-up for SWCLK. |
| 64 | P2_15 | bidirectional | GPIO port P2.15 that carries the SWD data line (SWDIO) with UART0_RXD, SPI_CS, I2C SDA, TIM2_CH1, CLUOUT1, EXTI15 and WK7 alternate functions, with a fixed-on 10kΩ pull-up for SWDIO. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | LINKOSEMI |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage AVDD (absolute maximum) | AVDD | -0.3 | 6 | V | 65 | ||
| Pre-driver supply voltage VCC (absolute maximum) | VCC | -0.3 | 25 | V | LKS07x with 6N driver | 65 | |
| Pre-driver supply voltage VCC (absolute maximum) | VCC | -0.3 | 40 | V | LKS07x with 3P3N driver | 65 | |
| LDO supply voltage VCCLDO (absolute maximum) | VCCLDO | -0.3 | 25 | V | LDO-supplied pins in 074DO | 65 | |
| Operating temperature | -40 | 105 | °C | 65 | |||
| Storage temperature | -40 | 150 | °C | 65 | |||
| Junction temperature | 125 | °C | 65 | ||||
| Lead temperature | 260 | °C | Soldering, 10 s | 65 | |||
| ESD HBM | -6000 | 6000 | V | MIL-STD-883J Method 3015.9, 25°C, 55% RH | 65 | ||
| Latch-up current | -200 | 200 | mA | 85°C, JEDEC JESD78E | 65 | ||
| Supply voltage AVDD (recommended) | AVDD | 2.5 | 5 | 5.5 | V | 65 | |
| Analog supply voltage AVDDA (recommended) | AVDDA | 2.8 | 5 | 5.5 | V | REF2VDD=0, ADC selects 2.4V internal reference | 65 |
| Analog supply voltage AVDDA (recommended) | AVDDA | 2.4 | 5 | 5.5 | V | REF2VDD=1, ADC selects AVDD as reference | 65 |
| GPIO signal input voltage range | VIN | -0.3 | 6 | V | 65 | ||
| Maximum injection current, single GPIO | IINJ_PAD | -11.2 | 11.2 | mA | 65 | ||
| Maximum injection current, all GPIO | IINJ_SUM | -50 | 50 | mA | 65 | ||
| Digital IO input high voltage | VIH | 3.06 | V | AVDD 5V | 66 | ||
| Digital IO input high voltage | VIH | 2.07 | V | AVDD 3.3V | 66 | ||
| Digital IO input low voltage | VIL | 0.8 | V | AVDD 3.3V | 66 | ||
| Digital IO input high current | IIH | 1 | uA | AVDD 5V / 3.3V | 66 | ||
| Digital IO input low current | IIL | -1 | uA | AVDD 5V / 3.3V | 66 | ||
| Digital IO output low voltage | VOL | 0.5 | V | Maximum drive current 11.2 mA | 66 | ||
| Pull-up resistor | Rpup | 8 | 12 | kΩ | Pull-up resistor (footnote * in datasheet) | 66 | |
| Resistance between IO and internal analog circuit | Rio-ana | 100 | 200 | Ω | 66 | ||
| Digital IO input capacitance | CIN | 10 | pF | AVDD 5V | 66 |
CAD (KiCad official)
- Symbol:
LKS32MC070RBT8 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
lks32mc070rbt8-etched.step/lks32mc070rbt8-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lks32mc070rbt8.step/lks32mc070rbt8.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: LINKOSEMI datasheet (91 pp, sha256
d7b5cc2187fa2830, retrieved 2026-10-19, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).