# LKS32MC037EM6S8B

**LINKOSEMI** · Microcontrollers (MCU/MPU/SOC) · SSOP-24

LKS32MC037EM6S8B from LINKOSEMI, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | AVDD | power_in | MCU low-voltage power supply, 2.5-5.5 V; it can be tied directly to the 5V LDO pin when heat dissipation is good, or driven from an external 5 V supply. |
| 2 | P0_4 | bidirectional | GPIO P0.4 with alternate functions including Hall input 0, ADC_CH1, CMP0_IP2, SPI_CS, SCL and EXTI2, and a built-in 10 kΩ pull-up that software can disable. |
| 3 | P0_5 | bidirectional | GPIO P0.5 with alternate functions including Hall input 1, MCPWM_BKIN1, UART0_TXD, SDA, TIM1_CH1, ADC_CH2, CMP0_IP1 and EXTI3, and a built-in 10 kΩ pull-up that software can disable. |
| 4 | P0_6 | bidirectional | GPIO P0.6 with alternate functions including Hall input 2, ADC_CH3, CMP0_IP0 and EXTI4; no internal pull-up is listed for this pin. |
| 5 | P0_8 | bidirectional | Datasheet lists P0.8 (CMP0_OUT, MCPWM_BKIN1, UART0_TXD, SPI_CLK, SCL, TIM0_CH0, ADC_TRIGGER, ADC_CH4, CMP0_IP3, PU, EXTI6, WK2) and P0.9 (CLKO, MCPWM_CH0P, UART0_RXD, SPI_DO, SDA, TIM0_CH1, ADC_TRIGGER, ADC_CH6, CMP0_IN, PU, EXTI7, WK3) under this single pin number; each has a built-in 10 kΩ pull-up that software can disable. |
| 6 | P0_7 | bidirectional | GPIO P0.7 with alternate functions including UART0_TXD, SCL, TIM0_CH1, ADC_CH5, OPAx_OUT and EXTI5, and a built-in 10 kΩ pull-up that software can disable. |
| 7 | LDO5V | power_out | 5 V LDO output, 4.75-5.25 V with 40 mA output capability for the G1 gate-driver module; connect a 1 µF decoupling capacitor close to the pin. |
| 8 | VCC | power_in | Gate-driver supply input, 7.5-28 V recommended operating range for the 037EM6S8(B/C). |
| 9 | HO1 | output | Phase U high-side gate-drive output (drives a PMOS, so low level is break-over), controlled by MCU P0.13 per the gate-driver schematic and requiring MCPWM_SWAP = 1. |
| 10 | LO1 | output | Phase U low-side gate-drive output, rated for a 10 V typical break-over level (8.5-11.5 V), controlled by MCU P0.10 per the gate-driver schematic. |
| 11 | HO2 | output | Phase V high-side gate-drive output (drives a PMOS, so low level is break-over), controlled by MCU P0.14 per the gate-driver schematic and requiring MCPWM_SWAP = 1. |
| 12 | LO2 | output | Phase V low-side gate-drive output, rated for a 10 V typical break-over level (8.5-11.5 V), controlled by MCU P0.11 per the gate-driver schematic. |
| 13 | HO3 | output | Phase W high-side gate-drive output (drives a PMOS, so low level is break-over), controlled by MCU P0.15 per the gate-driver schematic and requiring MCPWM_SWAP = 1. |
| 14 | LO3 | output | Phase W low-side gate-drive output, rated for a 10 V typical break-over level (8.5-11.5 V), controlled by MCU P0.12 per the gate-driver schematic. |
| 15 | GND | power_in | Ground for the MCU and gate-driver circuits. |
| 16 | P1_1 | bidirectional | GPIO P1.1 that is also the OPA0 positive input. |
| 17 | P1_2 | bidirectional | GPIO P1.2 that is also the OPA0 negative input. |
| 18 | P1_5 | bidirectional | GPIO P1.5 with alternate functions including SPI_DI, SCL, TIM1_CH1, ADC_CH8, OPA1_IN, CMP1_IP0 and EXTI11/WK5, and a built-in 10 kΩ pull-up that software can disable. |
| 19 | P1_3 | bidirectional | GPIO P1.3 with alternate functions including SPI_CS, TIM1_CH0 and OPA1_IP (OPA1 positive input). |
| 20 | P1_4 | bidirectional | GPIO P1.4 with alternate functions including CMP1_OUT, MCPWM_BKIN0, SPI_CS, TIM0_CH1, CMP1_IN and EXTI10, and a built-in 10 kΩ pull-up that software can disable. |
| 21 | P1_6 | bidirectional | Datasheet lists P1.6 (CMP1_OUT, HALL_IN1, MCPWM_CH2N, UART0_TXD, TIM0_CH1, ADC_TRIGGER, ADC_CH7, CMP1_IP2, PU, EXTI12) and P1.7 (CMP0_OUT, HALL_IN0, MCPWM_CH2P, UART0_RXD, TIM0_CH0, ADC_TRIGGER, CMP1_IP1, PU, EXTI13) under this single pin number; each has a built-in 10 kΩ pull-up that software can disable. |
| 22 | P1_8 | bidirectional | GPIO P1.8 that is also SWCLK (SWD clock, with internal 10 kΩ pull-up fixed on), with further alternate functions including HALL_IN2, MCPWM_CH3P, UART0_TXD, SCL, TIM1_CH0, ADC_TRIGGER, CMP1_IP3 and EXTI14/WK6. |
| 23 | P1_9 | bidirectional | GPIO P1.9 that is also SWDAT (SWD data, with internal 10 kΩ pull-up fixed on), with further alternate functions including MCPWM_CH3N, UART0_RXD, SDA, TIM1_CH1, ADC_CH9 and EXTI15/WK7. |
| 24 | P0_0 | bidirectional | Datasheet lists P0.0 (MCPWM_BKIN0, UART0_RXD, ADC_CH10, REF, LDO15, DAC_OUT, EXTI0, WK0) and P0.2 (SPI_DI, RST_n, PU, EXTI1, WK1) under this single pin number; P0.2 is RSTN by default and needs a 10 nF-100 nF capacitor to ground, with a 10 kΩ built-in pull-up that software can disable. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LINKOSEMI |
| Package | SSOP-24 |
| Category | Embedded Processors & Controllers |
| Pins | 24 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| MCU Supply Voltage (AVDD) | AVDD | -0.3 |  | 6 | V |  | 87 |
| Gate Driver Supply Voltage (VCC) | VCC | -0.3 |  | 40 | V |  | 87 |
| 5V LDO output current |  |  |  | 40 | mA | 037EM6S8(B/C) group; LDO maximum load 30mA, 5V case maximum load 15mA | 87 |
| Operating temperature |  | -40 |  | 105 | ˚C |  | 87 |
| Storage temperature |  | -40 |  | 150 | ˚C |  | 87 |
| Junction temperature |  |  |  | 125 | °C |  | 87 |
| Pin temperature |  |  |  | 260 | °C | Soldering for 10 sec | 87 |
| ESD test (HBM) MCU |  | -6000 |  | 6000 | V | HBM; 037EM6S8(B/C) group | 87 |
| ESD test (HBM) Gate driver |  | -2000 |  | 2000 | V | HBM; 037EM6S8(B/C) group | 87 |
| Latch-up current |  | -200 |  | 200 | mA | 85℃ | 88 |
| Input voltage range for GPIO signals | VIN | -0.3 |  | 6 | V |  | 88 |
| Maximum injection current for single GPIOs | IINJ_PAD | -11.2 |  | 11.2 | mA |  | 88 |
| Maximum injection current for all GPIOs | IINJ_SUM | -50 |  | 50 | mA |  | 88 |
| MCU Supply Voltage (AVDD) | AVDD | 2.5 | 5 | 5.5 | V |  | 87 |
| Analog Operating Voltage (AVDDA) | AVDDA | 2.8 | 5 | 5.5 | V | REF2VDD=0, ADC uses internal 2.4V reference | 87 |
| Analog Operating Voltage (AVDDA) | AVDDA | 2.4 | 5 | 5.5 | V | REF2VDD=1, ADC uses AVDD as reference | 87 |
| Gate Driver Supply Voltage (VCC) | VCC | 7.5 |  | 28 | V | 035DL6S8(B/C)/037EM6S8(B/C)/037QM6Q8(B/C)/039DK6Q8B(C) group | 87 |
| LDO Supply Voltage (VCCLDO) | VCCLDO | 5.6 |  | 28 | V |  | 87 |
| High input level of digital IO (VIH) | VIH | 3.04 |  |  | V | AVDD=5V | 88 |
| High input level of digital IO (VIH) | VIH | 2.05 |  |  | V | AVDD=3.3V | 88 |
| Low input level of digital IO (VIL) | VIL |  |  | 0.8 | V | AVDD=3.3V | 88 |
| Digital IO current when input is high (IIH) | IIH |  |  | 1 | uA | AVDD=5V | 88 |
| Digital IO current when input is low (IIL) | IIL | -1 |  |  | uA | AVDD=5V | 88 |
| Low output level of digital IO (VOL) | VOL |  |  | 0.5 | V | Current = 11.2mA | 88 |
| Pull-up resistor (Rpup) | Rpup | 8 |  | 12 | kΩ | Only part of IOs have built-in pull-up resistors | 88 |
| Connection resistance between IO and internal analog circuit (Rio-ana) | Rio-ana | 100 |  | 200 | Ω |  | 88 |
| Digital IO Input-capacitance (CIN) | CIN |  |  | 10 | pF | AVDD=5V | 88 |
| ADC supply voltage |  | 2.8 | 5 | 5.5 | V | REF2VDD=0, ADC uses internal 2.4V reference | 89 |
| ADC supply voltage |  | 2.4 | 5 | 5.5 | V | REF2VDD=1, ADC uses AVDD as reference | 89 |
| Differential input signal range |  | -2.4 |  | 2.4 | V | Gain=1; REF=2.4V | 89 |
| Differential input signal range |  | -3.6 |  | 3.6 | V | Gain=2/3; REF=3.6V | 89 |
| Single-ended input signal range |  | -0.3 |  |  | V | Limited by IO port input voltage | 89 |
| DC offset (ADC) |  |  | 5 | 10 | mV | Correctable | 89 |
| Effective number of bits (ENOB) | ENOB | 10.5 | 11 |  | bit |  | 89 |
| INL (ADC) | INL |  | 2 | 3 | LSB |  | 89 |
| DNL (ADC) | DNL |  | 1 | 2 | LSB |  | 89 |
| SNR (ADC) | SNR | 63 | 66 |  | dB |  | 89 |
| Reference supply voltage (REF) |  | 2.5 | 5 | 5.5 | V |  | 89 |
| Reference output deviation |  | -9 |  | 9 | mV |  | 89 |
| Supply voltage (DAC) |  | 2.5 | 5 | 5.5 | V |  | 89 |
| Output voltage range (DAC) |  | 0.05 |  | 3 | V |  | 89 |
| DNL (DAC) | DNL |  | 1 | 2 | LSB |  | 89 |
| INL (DAC) | INL |  | 2 | 4 | LSB |  | 89 |
| OFFSET (DAC) |  |  | 5 | 10 | mV |  | 89 |
| SNR (DAC) | SNR | 57 | 60 | 66 | dB |  | 89 |
| OPA supply voltage |  | 3.1 | 5 | 5.5 | V |  | 90 |
| OPA OFFSET |  |  | 10 | 15 | mV | OPA differential input short-circuited; OPA OUT measured from 0 level | 90 |
| OPA common mode voltage (Vcm) | Vcm | 1.65 |  | 2.15 | V | Measurement condition: normal temperature | 90 |
| OPA output signal range |  | 0.1 |  |  | V | Minimum load resistance | 90 |
| Comparator supply voltage (CMP) |  | 2.5 | 5 | 5.5 | V |  | 90 |

## CAD (KiCad official)

- Symbol: `LKS32MC037EM6S8B`
- Footprint: `Package_SO:SSOP-24_5.3x8.2mm_P0.65mm`
- 3D model: SSOP-24 (KiCad packages3D, STEP)
- 3D model files: `lks32mc037em6s8b-etched.step` / `lks32mc037em6s8b-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lks32mc037em6s8b.step` / `lks32mc037em6s8b.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LINKOSEMI datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590903148582694912) (118 pp, sha256 `1c32edb1f3151627`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lks32mc037em6s8b-datasheet.pdf)