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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

LKS32MC037EM6S8

LINKOSEMI · Microcontrollers (MCU/MPU/SOC) · SSOP-24

LKS32MC037EM6S8 from LINKOSEMI, in a SSOP-24. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	AVDD	power_in	Low-voltage MCU supply for the chip, rated 2.5 to 5.5 V; it can be tied directly to the 5 V LDO output on well-heatsinked designs or driven from an external 5 V supply to reduce power loss.
2	P0_4	bidirectional	General-purpose I/O with alternate functions HALL_IN0, MCPWM_CH1N, ADC_CH1, CMP0_IP2 and EXTI2, and an internal 10 kΩ pull-up that software can disable.
3	P0_5	bidirectional	General-purpose I/O with alternate functions HALL_IN1, MCPWM_BKIN1, ADC_CH2, CMP0_IP1 and EXTI3, and an internal 10 kΩ pull-up that software can disable.
4	P0_6	bidirectional	General-purpose I/O with alternate functions HALL_IN2, ADC_CH3, CMP0_IP0 and EXTI4; no internal pull-up is listed for this pin.
5	P0_8/P0_9	bidirectional	Shared pin carrying P0_8 (CMP0_OUT, MCPWM_BKIN1, SPI_CLK, SCL, TIM0_CH0, ADC_CH4, CMP0_IP3, EXTI6, WK2) and P0_9 (CLKO, MCPWM_CH0P, SPI_DO, SDA, TIM0_CH1, ADC_TRIGGER, CMP0_IN, EXTI7, WK3), both with an internal 10 kΩ pull-up that software can disable.
6	P0_7	bidirectional	General-purpose I/O with alternate functions UART0_TXD, SCL, TIM0_CH1, ADC_CH5, OPAx_OUT (op-amp output monitor), EXTI5 and an internal 10 kΩ pull-up that software can disable.
7	LDO5V	power_out	5 V LDO output pin that requires a 1 µF decoupling capacitor placed close to the pin.
8	VCC	power_in	Pre-driver supply input rated 7.5 to 28 V, requiring a decoupling capacitor of at least 1 µF between VCC and GND; above 20 V, AVDD is powered from the internal LDO5V output, and a 1 kΩ to 2 kΩ shunt resistor between VCC and AVDD is recommended.
9	HO1	output	Phase A high-side gate drive output that follows GPIO P0.13 (HO1 = P0.13) and requires MCPWM_SWAP = 1 to output PWM.
10	LO1	output	Phase A low-side gate drive output that follows GPIO P0.10 (LO1 = P0.10) and requires MCPWM_SWAP = 1 to output PWM.
11	HO2	output	Phase B high-side gate drive output that follows GPIO P0.14 (HO2 = P0.14) and requires MCPWM_SWAP = 1 to output PWM.
12	LO2	output	Phase B low-side gate drive output that follows GPIO P0.11 (LO2 = P0.11) and requires MCPWM_SWAP = 1 to output PWM.
13	HO3	output	Phase C high-side gate drive output that follows GPIO P0.15 (HO3 = P0.15) and requires MCPWM_SWAP = 1 to output PWM.
14	LO3	output	Phase C low-side gate drive output that follows GPIO P0.12 (LO3 = P0.12) and requires MCPWM_SWAP = 1 to output PWM.
15	GND	power_in	Chip ground; the datasheet strongly recommends tying multiple ground pins together on the PCB.
16	P1_1	bidirectional	GPIO that serves as the non-inverting input of op-amp 0 (OPA0_IP).
17	P1_2	bidirectional	GPIO that serves as the inverting input of op-amp 0 (OPA0_IN).
18	P1_5	bidirectional	General-purpose I/O with alternate functions SPI_DI, SCL, TIM1_CH1, ADC_CH8, OPA1_IN (op-amp 1 inverting input), CMP1_IP0, EXTI11 and WK5, with an internal 10 kΩ pull-up that software can disable.
19	P1_3	bidirectional	General-purpose I/O with alternate functions SPI_CS, TIM1_CH0 and OPA1_IP (op-amp 1 non-inverting input); no internal pull-up is listed for this pin.
20	P1_4	bidirectional	General-purpose I/O with alternate functions CMP1_OUT, MCPWM_BKIN0, SPI_CS, TIM0_CH1, CMP1_IN, EXTI10 and an internal 10 kΩ pull-up that software can disable.
21	P1_6/P1_7	bidirectional	Shared pin carrying P1_6 (CMP1_OUT, HALL_IN1, MCPWM_CH2N, UART0_TXD, TIM0_CH1, ADC_CH7, CMP1_IP2, EXTI12) and P1_7 (CMP0_OUT, HALL_IN0, MCPWM_CH2P, UART0_RXD, TIM0_CH0, CMP1_IP1, EXTI13), both with an internal 10 kΩ pull-up that software can disable.
22	P1_8	bidirectional	General-purpose I/O with alternate functions SWCLK (SWD clock), HALL_IN2, MCPWM_CH3P, UART0_TXD, SCL, TIM1_CH0, CMP1_IP3, EXTI14 and WK6, with an internal 10 kΩ pull-up that software can disable.
23	P1_9	bidirectional	General-purpose I/O with alternate functions SWDAT (SWD data), MCPWM_CH3N, UART0_RXD, SDA, TIM1_CH1, ADC_CH9, EXTI15 and WK7, with an internal 10 kΩ pull-up that software can disable.
24	P0_0/P0_2	bidirectional	Shared pin carrying P0_0 (MCPWM_BKIN0, UART0_RXD, ADC_CH10, REF, LDO15 1.5 V output, DAC_OUT, EXTI0, WK0) and P0_2 (SPI_DI, default RST_n reset input with a recommended 10 nF to 100 nF capacitor to ground and a 10 kΩ to 20 kΩ pull-up to AVDD, internal 10 kΩ pull-up, EXTI1, WK1).

Key specifications

Parameter	Value
Manufacturer	LINKOSEMI
Package	SSOP-24
Category	Embedded Processors & Controllers
Pins	24

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
MCU supply voltage	AVDD	-0.3		6	V		86
Pre-driver supply voltage	VCC	-0.3		40	V		86
LDO supply voltage	VCCLDO	-0.3		40	V	LDO-powered pins	86
5V LDO output current				40	mA		86
Operating temperature		-40		105	°C		86
Storage temperature		-40		150	°C		86
Junction temperature				125	°C		86
Pin temperature				260	°C	soldering, 10 s	86
MCU supply voltage	AVDD	2.5	5	5.5	V		86
Analog operating voltage	AVDDA	2.8	5	5.5	V	REF2VDD=0, ADC selects 2.4V internal reference	86
Analog operating voltage	AVDDA	2.4	5	5.5	V	REF2VDD=1, ADC selects AVDD as reference	86
Pre-driver supply voltage	VCC	7.5		28	V		86
LDO supply voltage	VCCLDO	5.6		28	V	LDO supply pins	86
ESD HBM, MCU		-6000		6000	V	HBM per MIL-STD-883J Method 3015.9, 25°C, 55% RH	87
ESD HBM, MOS/Driver		-2000		2000	V	HBM per MIL-STD-883J Method 3015.9, 25°C, 55% RH	87
Latch-up current		-200		200	mA	85°C, JEDEC JESD78E	87
GPIO signal input voltage range	VIN	-0.3		6	V		87
Single GPIO maximum injection current	IINJ_PAD	-11.2		11.2	mA		87
Total GPIO maximum injection current	IINJ_SUM	-50		50	mA		87
Digital IO input high voltage	VIH	3.04			V	AVDD 5V	87
Digital IO input high voltage	VIH	2.05			V	AVDD 3.3V	87
Digital IO input low voltage	VIL			0.8	V	AVDD 3.3V	87
Digital IO output low voltage	VOL			0.5	V	maximum drive current 11.2mA	87
Digital IO input high current	IIH			1	uA	AVDD 5V / 3.3V	87
Digital IO input low current	IIL	-1			uA	AVDD 5V / 3.3V	87
Pull-up resistor (partial IOs with built-in pull-up)	Rpup	8		12	kΩ	only some IOs have built-in pull-up	87
IO to internal analog circuit connection resistance	Rio-ana	100		200	Ω		87
Digital IO input capacitance	CIN			10	pF	AVDD 5V / 3.3V	88

CAD (KiCad official)

Symbol: LKS32MC037EM6S8
Footprint: Package_SO:SSOP-24_5.3x8.2mm_P0.65mm
3D model: SSOP-24 (KiCad packages3D, STEP)
3D model files: lks32mc037em6s8-etched.step / lks32mc037em6s8-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lks32mc037em6s8.step / lks32mc037em6s8.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: LINKOSEMI datasheet (115 pp, sha256 a7e82df9d09fcf8d, retrieved 2026-10-15, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF