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LHA7724SEQG

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Legendsemi Analog To Digital Converters (ADC), QFN-24-EP(4x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LHA7724SEQG

Legendsemi · Analog To Digital Converters (ADC) · QFN-24-EP(4x5)

LHA7724SEQG from Legendsemi, in a QFN-24-EP(4x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 DRDY output Active-low data-ready output, driven low when new conversion data is ready to be retrieved.
2 DOUT tri_state Serial interface data output, shifted out on SCLK falling edge and high-impedance when CS is high.
3 DIN input Serial interface data input, shifted in on SCLK rising edge.
4 CS input Active-low serial interface chip select.
5 SYNC input Synchronization input, active on the rising edge.
6 MFLAG output Modulator input-range overflow flag output, set high under over-range conditions.
7 DGND power_in Digital ground, connect to the digital ground plane.
8 AVSS power_in Negative analog supply, 0 V to -2.6 V relative to DGND.
9 REGCAPA passive Analog regulator capacitor pin; connect a capacitor of 100 nF or more (X7R).
10 AINP2 input Positive analog input 2.
11 AINN2 input Negative analog input 2.
12 AINP1 input Positive analog input 1.
13 AINN1 input Negative analog input 1.
14 AVDD power_in Positive analog supply, AVSS + 4.5 V to AVSS + 5.5 V.
15 AVSS power_in Negative analog supply, 0 V to -2.6 V relative to DGND.
16 VREFN input Negative reference input, AVSS - 0.1 V to VREFP - 1 V.
17 VREFP input Positive reference input, VREFN + 1 V to AVDD + 0.1 V.
18 PWDN input Active-low power-down input.
19 RESET input Active-low reset input; hold low at least 2/fCLK to force a reset.
20 DVDD power_in Digital supply, 1.65 V to 3.6 V.
21 DGND power_in Digital ground, connect to the digital ground plane.
22 REGCAPD power_out 1.8 V regulator output; connect a 1 uF capacitor to DGND.
23 CLK input Master clock input, 8.192 MHz specified (1 to 8.192 MHz).
24 SCLK input Serial interface clock input; hold low when inactive.
25 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Legendsemi
Package QFN-24-EP(4x5)
Category Data Acquisition
Pins 25

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD to AVSS -0.3 5.5 V 6
AVSS to DGND -2.8 0.3 V 6
DVDD to DGND -0.3 3.9 V 6
Input current, continuous -10 10 mA 6
Operating temperature (absolute maximum) -50 125 °C 6
Junction temperature 150 °C 6
Storage temperature Tstg -60 150 °C 6
ESD HBM VESD -2000 2000 V JEDEC JS-001 6
ESD CDM VESD -500 500 V JEDEC JESD22-C101 6
Negative analog supply AVSS -2.6 0 V relative to DGND 6
Digital supply DVDD 1.65 3.6 V relative to DGND 6
Clock input fCLK 1 8.192 MHz 6
Specified temperature -40 85 °C 6
Data rate, FIR filter mode fDATA 125 32000 SPS FIR filter mode 7
Data rate, SINC filter mode fDATA 16000 128000 SPS SINC filter mode 7
Integral nonlinearity INL -2.5 2.5 ppm 7
Offset voltage Offset -50 50 µV 7
Passband ripple -0.003 0.003 dB 7
Input leakage Ilkg -10 10 µA 0 < VDIGITAL IN < DVDD 8
CS low to SCLK high setup time tCSSC 40 ns 8
SCLK period tSCLK 2 16 1/fCLK 8
SCLK pulse duration, high and low tSPWH, L 0.8 10 1/fCLK 8
DIN valid to SCLK high setup time tDIST 50 ns 8
Valid DIN to SCLK high hold time tDIHD 50 ns 8
CS high pulse tCSH 100 ns 8
CLK high to CS high tSCCS 24 1/fCLK 8
CS low to DOUT drive propagation delay tCSDOD 60 ns 8
SCLK low to valid new DOUT propagation delay tDOPD 100 ns DOUT load = 20 pF 100 kΩ 8
SCLK low to DOUT invalid hold time tDOHD 0 ns 8
CS high to DOUT tri-state tCSDOZ 40 ns 8
Junction-to-ambient thermal resistance RθJA 30.2 °C/W 24-pin QFN 7
Junction-to-case (top) thermal resistance RθJC(top) 27.5 °C/W 24-pin QFN 7
Junction-to-board thermal resistance RθJB 8.5 °C/W 24-pin QFN 7
Junction-to-case (bottom) thermal resistance RθJC(bot) 1.7 °C/W 24-pin QFN 7
Multiplexer switch on-resistance 30 Ω 7
ADC input impedance, low-power mode 96 kΩ Low-power mode 7
ADC input impedance, high-resolution mode 48 kΩ High-resolution mode 7
SNR, low-power mode SNR 100.1 dB Low-power mode @64kHz 7
SNR, high-resolution mode SNR 95.5 dB High-resolution mode @128kHz 7
THD, low-power mode THD -111 dB Low-power mode 7
THD, high-resolution mode THD -111 dB High-resolution mode 7
Spurious-free dynamic range SFDR 112 dB 7
Resolution 24 Bits 7
Offset voltage after calibration 1 µV 7
Offset drift 25 nV/°C 7
Gain error 0.004 % 7
Gain error after calibration 0.0002 % 7
Gain drift 1 ppm/°C 7
Common-mode rejection ratio CMR 110 dB fCM = 60 Hz, 1.25 Vp-p 7
PSRR, AVDD/AVSS PSR 116 dB fPS = 60 Hz, 100mVPP, AVDD, AVSS 7
PSRR, DVDD PSR 125 dB fPS = 60 Hz, 100mVPP, DVDD 7
Reference input impedance, low-power mode 64 kΩ Low-power mode 7
Reference input impedance, high-resolution mode 32 kΩ High-resolution mode 7
Analog supply current, low-power mode IAVDD, IAVSS 0.75 mA Low-power mode 8
Analog supply current, high-resolution mode IAVDD, IAVSS 1.35 mA High-resolution mode 8
Analog supply current, standby mode IAVDD, IAVSS 0.35 µA Standby mode 8
Analog supply current, power-down mode IAVDD, IAVSS 0.35 µA Power-down mode 8
Digital supply current, low-power mode IDVDD 0.52 mA Low-power mode 8
Digital supply current, high-resolution mode IDVDD 0.72 mA High-resolution mode 8
Digital supply current, standby mode IDVDD 26 µA Standby mode 8
Digital supply current, power-down mode IDVDD 0.3 µA Power-down mode 8
Power dissipation, low-power mode PD 5.5 mW Low-power mode 8
Power dissipation, high-resolution mode PD 9.1 mW High-resolution mode 8

CAD (KiCad official)

  • Symbol: LHA7724SEQG
  • Footprint: Package_DFN_QFN:QFN-24-1EP_4x5mm_P0.5mm_EP2.65x3.65mm
  • 3D model: QFN-24-EP(4x5) (KiCad packages3D, STEP)
  • 3D model files: lha7724seqg-etched.step / lha7724seqg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lha7724seqg.step / lha7724seqg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Legendsemi datasheet (39 pp, sha256 fe3fc1d90c234ff8, retrieved 2026-10-23, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF