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LHA5115SGQL

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Legendsemi Analog To Digital Converters (ADC), QFN-40-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LHA5115SGQL

Legendsemi · Analog To Digital Converters (ADC) · QFN-40-EP(6x6)

LHA5115SGQL from Legendsemi, in a QFN-40-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VINCOM input Voltage input common; the reference for single-ended inputs, and it must be connected to analog ground.
2 VIN0 input Voltage input 0, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN1; inputs are ±10 V bipolar.
3 VIN1 input Voltage input 1, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN0; inputs are ±10 V bipolar.
4 VIN2 input Voltage input 2, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN3; inputs are ±10 V bipolar.
5 VIN3 input Voltage input 3, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN2; inputs are ±10 V bipolar.
6 REFOUT output Internal reference buffered output at 2.5 V with respect to AVSS; decouple to AVSS with a 0.1 µF capacitor.
7 REGCAPA output Analog LDO regulator output; decouple to AVSS with a 1 µF and a 0.1 µF capacitor.
8 AVSS power_in Negative analog supply, ranging from −2.75 V to 0 V and nominally set to 0 V.
9 AVDD power_in Analog supply voltage, ranging from 3.0 V to 5.5 V with respect to AVSS.
10 DNC unconnected Do not connect; nothing may be connected to this pin, and it is internally connected to AVSS.
11 VBIAS− input Voltage bias negative that sets the bias voltage for the voltage input AFE; connect to AVSS.
12 XTAL1 input Input 1 for the crystal oscillator.
13 XTAL2/CLKIO bidirectional Input 2 for crystal or clock input/output; its function is set by the CLOCKSEL bit in the ADC Mode Register.
14 DOUT/RDY output Serial data output and data-ready output; it is tristated when CS is high and goes low to flag conversion completion when CS is low and no register is being read.
15 DIN input Serial data input to the ADC input shift register, clocked in on the SCLK rising edge.
16 SCLK input Serial clock input for data transfers to and from the ADC, with a Schmitt-triggered input.
17 CS input Active-low chip select; it can be hardwired low for 3-wire operation, and DOUT/RDY is tristated when CS is high.
18 ERROR bidirectional Error input/output or general-purpose output, referenced between IOVDD and DGND, with function selected by the ERR_EN bits in the GPIOCON register.
19 SYNC input Synchronization input that allows digital filter and modulator synchronization when using multiple devices.
20 IOVDD power_in Digital input/output supply, ranging from 2 V to 5.5 V nominal and independent of AVDD; if AVSS is set to −2.5 V, IOVDD must not exceed 3.6 V.
21 DGND power_in Digital ground.
22 REGCAPD output Digital LDO regulator output, for decoupling only; decouple to DGND with a 1 µF capacitor.
23 GPIO0 bidirectional General-purpose input/output 0, with logic levels referred to AVDD and AVSS.
24 GPIO1 bidirectional General-purpose input/output 1, with logic levels referred to AVDD and AVSS.
25 GPO2 output General-purpose output 2, with logic levels referred to AVDD and AVSS.
26 VIN4 input Voltage input 4, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN5; inputs are ±10 V bipolar.
27 VIN5 input Voltage input 5, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN4; inputs are ±10 V bipolar.
28 VIN6 input Voltage input 6, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN7; inputs are ±10 V bipolar.
29 VIN7 input Voltage input 7, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN6; inputs are ±10 V bipolar.
30 VIN8 input Voltage input 8, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN9; inputs are ±10 V bipolar.
31 VIN9 input Voltage input 9, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN8; inputs are ±10 V bipolar.
32 VIN10 input Voltage input 10, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN11; inputs are ±10 V bipolar.
33 VIN11 input Voltage input 11, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN10; inputs are ±10 V bipolar.
34 VIN12 input Voltage input 12, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN13; inputs are ±10 V bipolar.
35 VIN13 input Voltage input 13, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN12; inputs are ±10 V bipolar.
36 VIN14 input Voltage input 14, referenced to VINCOM in single-ended mode or as the positive input of a differential pair with VIN15; inputs are ±10 V bipolar.
37 VIN15 input Voltage input 15, referenced to VINCOM in single-ended mode or as the negative input of a differential pair with VIN14; inputs are ±10 V bipolar.
38 GPO3 output General-purpose output 3, with logic levels referred to AVDD and AVSS.
39 REF− input Reference input negative terminal; the REF- voltage can span from AVSS to AVDD − 1 V and is selected through the REF_SELx bits.
40 REF+ input Reference input positive terminal for an external reference applied between REF+ and REF-; the datasheet states the REF+ voltage can span from AVDD to AVSS + 1 V and is selected through the REF_SELx bits.
41 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Legendsemi
Package QFN-40-EP(6x6)
Category Data Acquisition
Pins 41

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Differential Input Voltage Range -20 20 V Specified performance 6
Absolute Input Pin Voltage -20 20 V 6
Input Impedance 1 MΩ 6
Offset Error -0.4 0.4 mV TA = 25°C 6
Offset Drift -3 3 µV/°C 6
Gain Error -0.05 0.05 % FS TA = 25°C 6
Gain Drift -0.6 0.6 ppm/°C 6
Integral Nonlinearity (INL) -0.001 0.001 % FSR 6
Normal Mode Rejection 71 90 dB 50 Hz ±1 Hz and 60 Hz ±1 Hz, internal clock, 20 SPS ODR (postfilter) 6
Normal Mode Rejection 85 90 dB 50 Hz ±1 Hz and 60 Hz ±1 Hz, external clock, 20 SPS ODR (postfilter) 6
ADC Output Data Rate (ODR) 2.5 125000 SPS One channel, see Table 16 6
Initial Accuracy REFOUT -0.12 0.12 % REFOUT, TA = 25°C 6
Reference Temperature Coefficient (±3 value) -3 3 ppm/°C 6
Reference Temperature Coefficient (+12 value) 12 ppm/°C 6
Reference Load Current ILOAD -3 3 mA 6
External Reference Differential Input Range VREF 1 2.5 V VREF = (REF+) − (REF−) 6
External Reference Input Current -30 30 µA/V Buffers disabled 6
External Reference Input Current Drift -1 1 nA/V/°C Buffers disabled, external clock 6
External Reference Input Current Drift -3 3 nA/V/°C Buffers disabled, internal clock 6
External Reference Input Current -300 300 nA Buffers enabled 6
Temperature Sensor Accuracy -2 2 °C After user calibration at 25°C 7
Logic Input Leakage Current -10 10 µA 7
Logic Output Leakage Current -10 10 µA Floating state 7
Internal Clock Accuracy -2.5 2.5 % 7
Crystal Frequency 14 16 16.384 MHz 7
External Clock (CLKIO) Duty Cycle 30 50 70 % External clock (CLKIO) 7
AVDD to AVSS Power Supply Voltage 4.5 5.5 V 7
AVSS to DGND Power Supply Voltage -2.75 0 V 7
IOVDD to DGND Power Supply Voltage 2 5.5 V 7
AVDD Current 7.2 mA Full operating mode, including internal reference 7
Standby Mode Current 210 µA All VIN = 0 V 7
Power-Down Mode Current 185 µA All VIN = 0 V 7
SCLK High Pulse Width t3 25 ns SCLK high pulse width 8
SCLK Low Pulse Width t4 25 ns SCLK low pulse width 8
CS Falling Edge to DOUT/RDY Active Time t1 0 ns CS falling edge to DOUT/RDY active time 8
CS Falling Edge to DOUT/RDY Active Time t1 15 ns IOVDD = 4.75 V to 5.5 V 8
CS Falling Edge to DOUT/RDY Active Time t1 40 ns IOVDD = 2 V to 3.6 V 8
SCLK Active Edge to Data Valid Delay t2 0 ns SCLK active edge to data valid delay 8
SCLK Active Edge to Data Valid Delay t2 12.5 ns IOVDD = 4.75 V to 5.5 V 8
SCLK Active Edge to Data Valid Delay t2 25 ns IOVDD = 2 V to 3.6 V 8
Bus Relinquish Time after CS Inactive Edge t5 2.5 ns Bus relinquish time after CS inactive edge 8
Bus Relinquish Time after CS Inactive Edge t5 20 ns Bus relinquish time after CS inactive edge 8
SCLK Inactive Edge to CS Inactive Edge t6 0 ns SCLK inactive edge to CS inactive edge 8
SCLK Inactive Edge to DOUT/RDY High/Low t7 10 ns SCLK inactive edge to DOUT/RDY high/low 8
Data Valid to SCLK Edge Setup Time t9 8 ns Data valid to SCLK edge setup time 8
Data Valid to SCLK Edge Hold Time t10 8 ns Data valid to SCLK edge hold time 8
AVDD to AVSS -0.3 6.5 V TA = 25°C 9
AVDD to DGND -0.3 6.5 V TA = 25°C 9
IOVDD to DGND -0.3 6.5 V TA = 25°C 9
IOVDD to AVSS -0.3 7.5 V TA = 25°C 9
AVSS to DGND -3.25 0.3 V TA = 25°C 9
VINx to AVSS -65 65 V TA = 25°C 9
Digital Input Current 10 mA TA = 25°C 9
Operating Temperature Range TA -40 105 °C 9
Storage Temperature Range -65 150 °C 9
Maximum Junction Temperature TJ 150 °C 9
Lead Soldering, Reflow Temperature 260 °C 9

CAD (KiCad official)

  • Symbol: LHA5115SGQL
  • Footprint: Package_DFN_QFN:QFN-40-1EP_6x6mm_P0.5mm_EP4.6x4.6mm
  • 3D model: QFN-40-EP(6x6) (KiCad packages3D, STEP)
  • 3D model files: lha5115sgql-etched.step / lha5115sgql-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lha5115sgql.step / lha5115sgql.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Legendsemi datasheet (48 pp, sha256 18d520ec3a3bbaa9, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF