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LH32M0S32BLMG

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Legendsemi(领慧立芯) Microcontrollers (MCU/MPU/SOC), LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LH32M0S32BLMG

Legendsemi(领慧立芯) · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

LH32M0S32BLMG from Legendsemi(领慧立芯), in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CAP2 passive LCD charge-pump flying (charge-exchange) capacitor connection that the internal charge pump needs to generate VLCD.
2 CAP1 passive LCD charge-pump flying (charge-exchange) capacitor connection that the internal charge pump needs to generate VLCD.
3 NRST input External reset input, active low; a low level on this pin produces a system reset (pulse width at least 1.5 µs per the electrical table).
4 P0.2/AIN2/I2C_SDA/UART_TX/SPI_NSS/SWDIO bidirectional GPIO P0.2 with ADC input AIN2 and alternate functions I2C_SDA, UART_TX, SPI_NSS and the SWD data line SWDIO; after reset it defaults to SWDIO with a pull-up.
5 P0.3/AIN3/COMPN/I2C_SCL/UART_RX/SPI_SCLK/SWCLK bidirectional GPIO P0.3 with ADC input AIN3, analog comparator negative input COMPN and alternate functions I2C_SCL, UART_RX, SPI_SCLK and the SWD clock SWCLK; after reset it defaults to SWCLK with a pull-down.
6 VSSA power_in Analog ground for the ADC, reference and analog blocks.
7 VDDA power_in Analog supply; operating range 2.2 V to 3.6 V.
8 VREFN passive ADC reference ground, to be connected to analog ground.
9 VS/REFP power_in ADC regulator output that can also serve as the external reference input REFP; it can supply up to 8 mA to ground.
10 AIN0 passive ADC analog input channel AIN0.
11 AIN1 passive ADC analog input channel AIN1.
12 ACM/LVD/AIN4 passive 1.2 V reference (ACM) regulated output, shared with the low-voltage detect and analog comparator positive input and ADC input AIN4.
13 P0.4/AIN5/I2C_SDA bidirectional GPIO P0.4 with ADC input AIN5 and I2C_SDA alternate function.
14 P0.5/AIN6/PWM2/I2C_SCL bidirectional GPIO P0.5 with ADC input AIN6, PWM2 output and I2C_SCL alternate function.
15 P0.6/AIN7/UART_TX/LVD bidirectional GPIO P0.6 with ADC input AIN7, UART_TX and low-voltage detect input LVD.
16 P0.7/UART_RX/COMPOUT bidirectional GPIO P0.7 with UART_RX and analog comparator output COMPOUT.
17 P0.0/BZ/QSPI_CLK bidirectional GPIO P0.0 with beeper output BZ and QSPI clock QSPI_CLK; input enable cannot be turned off on P0.0-P0.7 and P1.0-P1.2, so pull or fixed level is advised during sleep.
18 P0.1/SPI_MOSI/PWM6/QSPI_NSS bidirectional GPIO P0.1 with SPI_MOSI, PWM6 output and QSPI chip select QSPI_NSS.
19 P1.0/SPI_MISO/PWM5/QSPI_IO0 bidirectional GPIO P1.0 with SPI_MISO, PWM5 output and QSPI data line QSPI_IO0.
20 P1.1/SPI_SCLK/PWM4/QSPI_IO1 bidirectional GPIO P1.1 with SPI_SCLK, PWM4 output and QSPI data line QSPI_IO1.
21 P1.2/SPI_NSS/PWM3/QSPI_IO2 bidirectional GPIO P1.2 with SPI_NSS, PWM3 output and QSPI data line QSPI_IO2.
22 P1.3/SEG20/PWM1/QSPI_IO3 bidirectional GPIO P1.3 with LCD segment SEG20, PWM1 output and QSPI data line QSPI_IO3.
23 P1.4/SEG19/SCLK_SPI bidirectional GPIO P1.4 with LCD segment SEG19 and SPI clock SCLK_SPI.
24 P1.5/SEG18/SPI_NSS/XIN bidirectional GPIO P1.5 with LCD segment SEG18, SPI chip select and the 32.768 kHz crystal input XIN.
25 P1.6/SEG17/I2C_SCL/GPIO_CLK/BZ/COMPOUT/XOUT bidirectional GPIO P1.6 with LCD segment SEG17, I2C_SCL, GPIO clock, beeper output BZ, comparator output COMPOUT and the 32.768 kHz crystal output XOUT.
26 P1.7/SEG16/I2C_SDA/SPI_MISO/BZn bidirectional GPIO P1.7 with LCD segment SEG16, I2C_SDA, SPI_MISO and the complementary beeper output BZn.
27 P2.0/SEG15/UART_TX/SPI_MOSI/PWM7/BZ bidirectional GPIO P2.0 with LCD segment SEG15, UART_TX, SPI_MOSI, PWM7 output and beeper output BZ.
28 P2.1/SEG14/UART_RX/PWM2/SPI_MISO bidirectional GPIO P2.1 with LCD segment SEG14, UART_RX, PWM2 output and SPI_MISO.
29 P2.2/SEG13/LED8/BZ/PWM1/SPI_SCLK bidirectional GPIO P2.2 with LCD segment SEG13, LED driver output LED8, beeper output BZ, PWM1 output and SPI_SCLK.
30 P2.3/SEG12/LED7/SPI_MOSI/PWM6 bidirectional GPIO P2.3 with LCD segment SEG12, LED driver output LED7, SPI_MOSI and PWM6 output.
31 P2.4/SEG11/LED6/SPI_MISO/PWM5 bidirectional GPIO P2.4 with LCD segment SEG11, LED driver output LED6, SPI_MISO and PWM5 output.
32 P2.5/SEG10/LED5/SPI_SCLK/PWM4 bidirectional GPIO P2.5 with LCD segment SEG10, LED driver output LED5, SPI_SCLK and PWM4 output.
33 P2.6/SEG9/LED4/SPI_NSS/PWM3 bidirectional GPIO P2.6 with LCD segment SEG9, LED driver output LED4, SPI_NSS and PWM3 output.
34 P2.7/SEG8/LED3/GPIO_CLK/TM1_BKIN bidirectional GPIO P2.7 with LCD segment SEG8, LED driver output LED3, GPIO clock input and Timer1 break input TM1_BKIN; it is also an HSE external clock input option (AF3).
35 P3.0/SEG7/LED2/PWM1 bidirectional GPIO P3.0 with LCD segment SEG7, LED driver output LED2 and PWM1 output.
36 P3.1/SEG6/LED1/PWM2 bidirectional GPIO P3.1 with LCD segment SEG6, LED driver output LED1 and PWM2 output.
37 P3.2/SEG5 bidirectional GPIO P3.2 with LCD segment SEG5.
38 P3.3/SEG4/UART_CTS bidirectional GPIO P3.3 with LCD segment SEG4 and UART_CTS.
39 P3.4/SEG3/UART_RTS bidirectional GPIO P3.4 with LCD segment SEG3 and UART_RTS.
40 P3.5/SEG2/QSP_NSS/UART_RX/PWM7 bidirectional GPIO P3.5 with LCD segment SEG2, QSPI chip select, UART_RX and PWM7 output.
41 P3.6/SEG1/QSPI_SCLK/UART_TX/TM1_BKIN bidirectional GPIO P3.6 with LCD segment SEG1, QSPI clock, UART_TX and Timer1 break input TM1_BKIN.
42 P3.7/COM4/QSPI_IO0/BZ bidirectional GPIO P3.7 with LCD common output COM4, QSPI data line QSPI_IO0 and beeper output BZ.
43 P4.0/COM3/QSPI_IO1/BZn bidirectional GPIO P4.0 with LCD common output COM3, QSPI data line QSPI_IO1 and complementary beeper output BZn.
44 P4.1/COM2/QSPI_IO2 bidirectional GPIO P4.1 with LCD common output COM2 and QSPI data line QSPI_IO2.
45 P4.2/COM1/QSPI_IO3/COMPOUT bidirectional GPIO P4.2 with LCD common output COM1, QSPI data line QSPI_IO3 and analog comparator output COMPOUT.
46 VSS power_in Digital ground.
47 VDD power_in Digital supply; operating range 2.2 V to 3.6 V.
48 VLCD power_in LCD drive supply: with the internal charge pump enabled an external capacitor is connected on VLCD_LED; with the charge pump off, VLCD is internally shorted to VDD.

Key specifications

Parameter Value
Manufacturer Legendsemi(领慧立芯)
Package LQFP-48(7x7)
Category Embedded Processors & Controllers
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
AVDD voltage between AVDD and AGND AVDD -0.3 3.9 V 230
DVDD voltage between DVDD and DGND DVDD -0.3 3.9 V 230
AGND voltage between AGND and IOGND AGND -0.3 0.3 V 230
DGND voltage between DGND and IOGND DGND -0.3 0.3 V 230
Voltage between VREFP and VREFN VCAP -0.3 3.9 V 230
IO pin voltage VIO -0.3 3.9 V 230
Storage temperature Tstorage -65 150 ℃ 230
Junction temperature Tjunction -40 125 ℃ 230
Sink current into any IO pin Isink 25 mA 230
Source current out of any IO pin Isource -25 mA 230
Total sink current into all IO pins Isink_tot 80 mA 230
Total source current out of all IO pins Isource_tot -80 mA 230
AVDD operating voltage range AVDD 2.2 3.6 V 230
DVDD operating voltage range DVDD 2.2 3.6 V 230
Chip operating temperature Ta -40 105 ℃ 230
Chip junction temperature Tj -40 125 ℃ 230
MCU clock frequency Fclk 0 32 MHz 230
IO input voltage range VIO -0.3 3.6 V 230
IO supply voltage DVDD 2.2 3.3 3.6 V 230
Input high-level voltage VIH 2.2 V 230
Input low-level voltage VIL -0.3 0.8 V 230
Input leakage current IL -10 10 µA 230
32kHz LRC oscillator frequency accuracy Faccuray_LRC -3 3 % 231

CAD (KiCad official)

  • Symbol: LH32M0S32BLMG
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: lh32m0s32blmg-etched.step / lh32m0s32blmg-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lh32m0s32blmg.step / lh32m0s32blmg.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Legendsemi(领慧立芯) datasheet (237 pp, sha256 68e4fc70a88a0840, retrieved 2026-11-07, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF