# LGS5145

**Legend-Si** · DC-DC Converters · SOT-23-6

LGS5145 from Legend-Si, in a SOT-23-6. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | BST | power_out | Bootstrap gate driver power supply: a high-quality 100nF ceramic capacitor must be connected between BST and SW to bias the internal high-side gate driver, and the capacitor's withstanding voltage must be checked (Pin to GND voltage range is -0.3V to SW+6V). |
| 2 | GND | power_in | Ground pin; the datasheet recommends a large copper-clad area for high-current GND paths. |
| 3 | FB | input | Feedback input connected to an external resistor divider; the internal comparator reference voltage is 0.812V (VFB 0.792V to 0.832V), and the pin is rated -0.3V to 6V to GND. |
| 4 | EN | input | Regulator enable pin: driving it high enables the output and driving it low turns the regulator off (rising threshold above 1.4V, falling threshold below 1V); it has a weak internal pull-down and should not be left floating, and its voltage rating is the same as VIN. |
| 5 | VIN | power_in | Regulator power input, recommended operating range 5V to 55V; bypass to GND with a 2.2µF or larger ceramic capacitor placed as close as possible to the pin. |
| 6 | SW | output | Internal power switching node, connected externally to the power inductor, Schottky diode, and BST capacitor; the pin is rated -0.3V to 60V to GND. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Legend-Si |
| Package | SOT-23-6 |
| Category | Power Supply Chip |
| Pins | 6 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN Recommended Input Voltage Range | VIN | 5 |  | 55 | V |  | 3 |
| Junction temperature range (TJ) | TJ | -40 |  | 125 | ℃ | Limit values apply to working junction temperature range | 3 |
| FB Feedback Voltage | VFB | 0.792 | 0.812 | 0.832 | V |  | 3 |
| switching frequency | FSW | 1 | 1.2 | 1.4 | Mhz | PWM Operation | 3 |
| Maximum Duty Cycle | DMAX | 90 | 94 |  | % |  | 3 |
| Pin to GND Voltage (VIN,SW,EN) |  | -0.3 |  | 60 | V |  | 2 |
| Pin to GND Voltage (BST) |  | -0.3 |  |  | V | Printed maximum is SW+6V (not numeric) | 2 |
| Pin to GND Voltage (FB) |  | -0.3 |  | 6 | V |  | 2 |
| Storage temperature |  | -65 |  | 150 | ℃ |  | 2 |
| operating temperature |  | -40 |  | 105 | ℃ |  | 2 |
| ESD Rating (HBM) |  | -3 |  | 3 | KV | HBM | 2 |
| ESD Rating (CDM) |  | -1 |  | 1 | KV | CDM | 2 |
| ESD Rating (MM) |  | -500 |  | 500 | V | MM | 2 |
| Input undervoltage lockout | VUVLO |  | 4.2 |  | V | Rising | 3 |
| Input undervoltage lockout | VUVLO |  | 3.5 |  | V | Falling | 3 |
| Static operating current | lQ |  | 150 |  | uA | No load,VIN=12V, not switching | 3 |
| Shutdown Current | IS |  | 4 |  | uA | EN=0,VIN=12V | 3 |
| BUCK upper tube RDSON | RDS(ON) |  | 600 |  | mΩ | TJ= 25℃ | 3 |
| Burp switching frequency | FSW_FB |  | 300 |  | Khz | EN=1,FB=0.1V | 3 |
| EN delay | TD.EN |  | 60 |  | uS | EN=0 EN=1 | 3 |
| Minimum on-time | TON.MIN |  | 60 |  | nA |  | 3 |
| soft start time | tSS |  | 2.4 |  | mS |  | 3 |
| FB bias current | IFB.BIAS |  | 5 |  | nA |  | 3 |
| SW leakage current | ISW.LKG |  | 1 |  | uA |  | 3 |
| SW Current Limit | lLIMIT.SW(Peak) |  | 1.2 |  | A |  | 3 |
| Input EN high logic threshold | VEN_H |  | 1.4 |  | V | 4.5V≤VIN≤52V | 3 |
| Input EN low logic threshold | VEN_L |  | 1 |  | V | 4.5V≤VIN≤52V | 3 |
| EN Input Current | ILKG-EN |  | 1 |  | uA | 4.5V≤VIN≤52V | 3 |
| overtemperature protection | TOTP-R |  | 150 |  | ℃ | TJ Rising | 3 |
| Over-temperature protection release | TOTP-F |  | 130 |  | ℃ | TJ Falling | 3 |
| Thermal resistivity from silicon core to surrounding air | θJA |  | 173 |  | ℃/W | 0 LFPM Air Flow | 3 |
| Thermal resistivity of silicon core to PCB board surface | θJB |  | 33.2 |  | ℃/W |  | 3 |
| Coefficient of thermal resistance from silicon core to package upper surface | θJCtop |  | 116 |  | ℃/W |  | 3 |
| Thermal resistivity of silicon core to PCB board surface | ΨJB |  | 30 |  | ℃/W |  | 3 |

## Materials and finish

As the datasheet states them (page.json `metadata.appearance`; the 3D model's colours follow it).

| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper |  | (PIN5) and GND (PIN2) pins to minimize high￾frequency noise ■ For high current paths, a larger PCB copper-clad | 14 |

## CAD (KiCad official)

- Symbol: `LGS5145`
- Footprint: `Package_TO_SOT_SMD:SOT-23-6`
- 3D model: SOT-23-6 (KiCad packages3D, STEP)
- 3D model files: `lgs5145-etched.step` / `lgs5145-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lgs5145.step` / `lgs5145.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Legend-Si datasheet](docs/lgs5145-datasheet.pdf) (17 pp, sha256 `4986d47d2af14ec7`, retrieved 2026-10-21, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lgs5145-datasheet.pdf)