component
LGS2752B5
Public Made by Adomby adom
Legend Si Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, SOT-23-5. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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LGS2752B5
Legend Si · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LGS2752B5 from Legend Si, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input pin; input voltage range is 6 V to 50 V, with an absolute maximum of 60 V VIN-to-GND (-0.3 V to 60 V). |
| 2 | GND | power_in | Power ground pin, the reference for all voltage ratings in the datasheet. |
| 3 | EN | input | Enable pin: high or floating enables the output, low puts the regulator in shutdown; EN absolute maximum is -0.3 V to 7 V (recommended 2 V to 6 V), with an internal pull-up and EN rising/falling thresholds of 1.5 V / 1 V. |
| 4 | NC | unconnected | No-connect pin; no external component is required, and it may be left floating or tied to ground. |
| 5 | VOUT | power_out | Regulated 5 V output; it must be bypassed to GND with a 1 µF or larger ceramic capacitor (2 µF to 4.7 µF recommended) for stability, with an absolute maximum of -0.3 V to 7 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Legend Si |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND voltage | VIN | -0.3 | 60 | V | 2 | ||
| EN to GND voltage | EN | -0.3 | 7 | V | 2 | ||
| VOUT to GND voltage | VOUT | -0.3 | 7 | V | 2 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 2 | ||
| Junction temperature | TJ | -40 | 125 | ℃ | 2 | ||
| ESD Human-body model | VESD | -2000 | 2000 | V | HBM, per JEDEC JS-001 | 3 | |
| ESD Charged-device model | VESD | -200 | 200 | V | CDM, per JESD22-C101 | 3 | |
| VIN to GND voltage | VIN | 6 | 50 | V | 3 | ||
| EN to GND voltage | EN | 2 | 6 | V | 3 | ||
| Junction temperature | TJ | -40 | 125 | ℃ | 3 | ||
| VIN input voltage range | VIN | 5.5 | 6 | 50 | V | 3 | |
| Load current | IOUT | 0 | 15 | 17 | mA | Output remains regulated at no load | 3 |
| Power supply rejection ratio | PSRR | 30 | 40 | dB | F=1-20KHz, IOUT=10mA | 3 | |
| Shutdown current | ISD | 10 | 18 | µA | EN=0V | 3 | |
| Output voltage | VOUT | 5 | V | 3 | |||
| Quiescent current | IQ | 40 | µA | 3 | |||
| Linear regulation | ΔVOUT | 0.04 | %/V | IOUT=10mA | 3 | ||
| Load regulation | 0.02 | µV/mA | IOUT=0mA to 15mA | 3 | |||
| EN rising threshold | VEN_R | 1.5 | V | 3 | |||
| EN falling threshold | VEN_F | 1 | V | 3 | |||
| Line transient response | 60 | mV | VIN=6-12V | 3 | |||
| Load transient response | 60 | mV | IOUT=5mA to 15mA | 3 | |||
| Thermal shutdown | TSD | 150 | ℃ | Design parameter, not production-tested | 3 | ||
| Thermal shutdown hysteresis | TSD_H | 25 | ℃ | Design parameter, not production-tested | 3 | ||
| Startup time, VOUT rise to 60% | TON1 | 140 | µs | VOUT rising to 60% | 4 | ||
| Startup time, VOUT rise to 95% | TON2 | 280 | µs | VOUT rising to 95% | 4 | ||
| Turn-off time, VOUT fall to 40% | TOFF1 | 20 | µs | VOUT falling to 40% | 4 | ||
| Turn-off time, VOUT fall to 5% | TOFF2 | 50 | µs | VOUT falling to 5% | 4 |
CAD (KiCad official)
- Symbol:
LGS2752B5 - Footprint:
Package_TO_SOT_SMD:SOT-23-5 - 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files:
lgs2752b5-etched.step/lgs2752b5-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);lgs2752b5.step/lgs2752b5.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Legend Si datasheet (9 pp, sha256
e319e514080edcdd, retrieved 2026-10-17, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# LGS2752B5
**Legend Si** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · SOT-23-5
LGS2752B5 from Legend Si, in a SOT-23-5. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VIN | power_in | Power input pin; input voltage range is 6 V to 50 V, with an absolute maximum of 60 V VIN-to-GND (-0.3 V to 60 V). |
| 2 | GND | power_in | Power ground pin, the reference for all voltage ratings in the datasheet. |
| 3 | EN | input | Enable pin: high or floating enables the output, low puts the regulator in shutdown; EN absolute maximum is -0.3 V to 7 V (recommended 2 V to 6 V), with an internal pull-up and EN rising/falling thresholds of 1.5 V / 1 V. |
| 4 | NC | unconnected | No-connect pin; no external component is required, and it may be left floating or tied to ground. |
| 5 | VOUT | power_out | Regulated 5 V output; it must be bypassed to GND with a 1 µF or larger ceramic capacitor (2 µF to 4.7 µF recommended) for stability, with an absolute maximum of -0.3 V to 7 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Legend Si |
| Package | SOT-23-5 |
| Category | Power Management (PMIC) |
| Pins | 5 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VIN to GND voltage | VIN | -0.3 | | 60 | V | | 2 |
| EN to GND voltage | EN | -0.3 | | 7 | V | | 2 |
| VOUT to GND voltage | VOUT | -0.3 | | 7 | V | | 2 |
| Storage temperature | Tstg | -65 | | 150 | ℃ | | 2 |
| Junction temperature | TJ | -40 | | 125 | ℃ | | 2 |
| ESD Human-body model | VESD | -2000 | | 2000 | V | HBM, per JEDEC JS-001 | 3 |
| ESD Charged-device model | VESD | -200 | | 200 | V | CDM, per JESD22-C101 | 3 |
| VIN to GND voltage | VIN | 6 | | 50 | V | | 3 |
| EN to GND voltage | EN | 2 | | 6 | V | | 3 |
| Junction temperature | TJ | -40 | | 125 | ℃ | | 3 |
| VIN input voltage range | VIN | 5.5 | 6 | 50 | V | | 3 |
| Load current | IOUT | 0 | 15 | 17 | mA | Output remains regulated at no load | 3 |
| Power supply rejection ratio | PSRR | 30 | 40 | | dB | F=1-20KHz, IOUT=10mA | 3 |
| Shutdown current | ISD | | 10 | 18 | µA | EN=0V | 3 |
| Output voltage | VOUT | | 5 | | V | | 3 |
| Quiescent current | IQ | | 40 | | µA | | 3 |
| Linear regulation | ΔVOUT | | 0.04 | | %/V | IOUT=10mA | 3 |
| Load regulation | | | 0.02 | | µV/mA | IOUT=0mA to 15mA | 3 |
| EN rising threshold | VEN_R | | 1.5 | | V | | 3 |
| EN falling threshold | VEN_F | | 1 | | V | | 3 |
| Line transient response | | | 60 | | mV | VIN=6-12V | 3 |
| Load transient response | | | 60 | | mV | IOUT=5mA to 15mA | 3 |
| Thermal shutdown | TSD | | 150 | | ℃ | Design parameter, not production-tested | 3 |
| Thermal shutdown hysteresis | TSD_H | | 25 | | ℃ | Design parameter, not production-tested | 3 |
| Startup time, VOUT rise to 60% | TON1 | | 140 | | µs | VOUT rising to 60% | 4 |
| Startup time, VOUT rise to 95% | TON2 | | 280 | | µs | VOUT rising to 95% | 4 |
| Turn-off time, VOUT fall to 40% | TOFF1 | | 20 | | µs | VOUT falling to 40% | 4 |
| Turn-off time, VOUT fall to 5% | TOFF2 | | 50 | | µs | VOUT falling to 5% | 4 |
## CAD (KiCad official)
- Symbol: `LGS2752B5`
- Footprint: `Package_TO_SOT_SMD:SOT-23-5`
- 3D model: SOT-23-5 (KiCad packages3D, STEP)
- 3D model files: `lgs2752b5-etched.step` / `lgs2752b5-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lgs2752b5.step` / `lgs2752b5.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Legend Si datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590931353888239616) (9 pp, sha256 `e319e514080edcdd`, retrieved 2026-10-17, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/lgs2752b5-datasheet.pdf)