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LF60CDT-TR

STMicroelectronics · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DPAK

LF60CDT-TR from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 INPUT power_in Regulator input; operating input voltage up to 16 V (absolute maximum -0.5 to 40 V, regulator in shutdown for 18 < VI < 40 V).
2 GND power_in Ground pin; the DPAK tab is electrically connected to GND, and in the three-terminal version the device is fixed in the ON state.
3 OUTPUT power_out Regulated 6 V output (LF60) delivering up to 500 mA, requires an output capacitor of 2 to 10 µF (ESR 0.1 to 10 Ω) for stability.

Key specifications

Parameter Value
Manufacturer STMicroelectronics
Package DPAK
Category Power Management (PMIC)
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Output voltage VO 5.88 6 6.12 V IO = 50 mA, VI = 8 V 23
Output voltage over temperature VO 5.76 6.24 V IO = 50 mA, VI = 8 V, Ta = -25 to 85 °C 23
Operating input voltage VI 16 V IO = 500 mA 23
Line regulation ∆VO 6 30 mV VI = 7 to 16 V, IO = 5 mA 23
Load regulation ∆VO 6 30 mV VI = 7.3 V, IO = 5 to 500 mA 23
Quiescent current ON mode Id 0.7 1.5 mA VI = 7 to 16 V, IO = 0 mA, ON mode 23
Quiescent current ON mode at full load Id 12 mA VI = 7.3 to 16 V, IO = 500 mA 23
Quiescent current OFF mode Id 70 140 µA VI = 9 V, OFF mode 23
Supply voltage rejection f=120 Hz SVR 75 dB IO = 5 mA, VI = 8 ± 1 V, f = 120 Hz 23
Supply voltage rejection f=1 kHz SVR 70 dB IO = 5 mA, VI = 8 ± 1 V, f = 1 kHz 23
Supply voltage rejection f=10 kHz SVR 60 dB IO = 5 mA, VI = 8 ± 1 V, f = 10 kHz 23
Output noise voltage eN 50 µV B = 10 Hz to 100 kHz 23
Dropout voltage at 200 mA Vd 0.2 0.35 V IO = 200 mA 23
Dropout voltage at 500 mA Vd 0.4 0.7 V IO = 500 mA 23
Output current limit IO 1 A 23
Control input logic high VIH 2 V Ta = -40 to 125 °C 23
Control input logic low VIL 0.8 V Ta = -40 to 125 °C 23
Control input current II 10 µA VI = 9 V, VC = 6 V 23
Output bypass capacitance CO 2 10 µF ESR = 0.1 to 10 Ω, IO = 0 to 500 mA 23
Absolute maximum DC input voltage VI -0.5 40 V 5
Storage temperature range TSTG -40 150 °C 5
Operating junction temperature range TOP -40 125 °C 5
Thermal resistance junction-case (DPAK) RthJC 8 °C/W DPAK/PPAK 5
Thermal resistance junction-ambient (DPAK) RthJA 100 °C/W DPAK/PPAK 5

CAD (KiCad official)

  • Symbol: LF60CDT-TR
  • Footprint: Package_TO_SOT_SMD:TO-252-2
  • 3D model: DPAK (KiCad packages3D, STEP)
  • 3D model files: lf60cdt-tr-etched.step / lf60cdt-tr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lf60cdt-tr.step / lf60cdt-tr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: STMicroelectronics datasheet (53 pp, sha256 307003c143a6294f, retrieved 2026-10-21, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF