component
LF50ABDT-TRY
Public Made by Adomby adom
STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DPAK. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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README.mdadded+39@@ -0,0 +1,39 @@+# LF50ABDT-TRY++**STMicroelectronics** · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · DPAK++LF50ABDT-TRY from STMicroelectronics, in a DPAK. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.++## Pinout++| Pin | Name | Type | Function |+|---|---|---|---|+| 1 | INPUT | power_in | Unregulated DC input supply pin to the regulator; per Figure 2 pin connections this lead is labeled INPUT (bottom lead, opposite side from the tab). |+| 2 | GND | power_in | Ground reference pin; the datasheet states the package TAB is electrically connected to GND on the DPAK package. |+| 3 | OUTPUT | power_out | Regulated output voltage pin, labeled OUTPUT (top lead) in Figure 2 pin connections. |++## Key specifications++| Parameter | Value |+|---|---|+| Manufacturer | STMicroelectronics |+| Package | DPAK |+| Category | Power Management (PMIC) |+| Pins | 3 |++## CAD (KiCad official)++- Symbol: `LF50ABDT-TRY`+- Footprint: `Package_TO_SOT_SMD:TO-252-2`+- 3D model: DPAK (KiCad packages3D, STEP)+- 3D model files: `lf50abdt-try-etched.step` / `lf50abdt-try-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lf50abdt-try.step` / `lf50abdt-try.glb` are the bare package body.++## Provenance++Data extracted from the manufacturer datasheet, not a distributor listing:++- **Datasheet:** [STMicroelectronics datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943619692900352) (53 pp, sha256 `1867ecd27e7bf609`, retrieved 2026-09-23, tier: lcsc)+- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-sonnet-5` (text+vision), consensus `claude-opus-4-8` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.+- **CAD:** KiCad official libraries (CC-BY-SA 4.0).++[Datasheet PDF](docs/lf50abdt-try-datasheet.pdf)
page.jsonadded+114@@ -0,0 +1,114 @@+{+ "slug": "lf50abdt-try",+ "version": "0.1.0",+ "type": "component",+ "description": "STMicroelectronics Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, DPAK. Datasheet-verified pinout, KiCad symbol/footprint/3D.",+ "tags": [+ "component",+ "power management (pmic)",+ "lf50abdt-try",+ "factory-2.0.0",+ "extractor-text"+ ],+ "dependencies": {},+ "hero": {+ "type": "image",+ "path": "docs/hero.png"+ },+ "files": [+ "page.json",+ "README.md",+ "lf50abdt-try.kicad_sym",+ "lf50abdt-try.kicad_mod",+ "lf50abdt-try.glb",+ "lf50abdt-try.step",+ "lf50abdt-try.lbr",+ "docs/hero.png",+ "docs/lf50abdt-try-datasheet.pdf",+ "viewers/symbol.html",+ "viewers/footprint.html"+ ],+ "component": {+ "mpn": "LF50ABDT-TRY",+ "manufacturer": "STMicroelectronics",+ "package": "DPAK",+ "pin_count": 3,+ "category": "Power Management (PMIC)",+ "subcategory": "Voltage Regulators - Linear, Low Drop Out (LDO) Regulators",+ "datasheet": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943619692900352",+ "parts": {+ "symbol": "lf50abdt-try.kicad_sym",+ "footprint": "lf50abdt-try.kicad_mod",+ "model_3d": "lf50abdt-try-etched.glb",+ "model_3d_plain": "lf50abdt-try.glb",+ "model_3d_step": "lf50abdt-try-etched.step",+ "model_3d_step_plain": "lf50abdt-try.step",+ "lbr": "lf50abdt-try.lbr"+ },+ "distributor_links": {+ "lcsc": "C2688670"+ },+ "pins": [+ {+ "number": "1",+ "name": "INPUT",+ "type": "power_in",+ "description": "Unregulated DC input supply pin to the regulator; per Figure 2 pin connections this lead is labeled INPUT (bottom lead, opposite side from the tab)."+ },+ {+ "number": "2",+ "name": "GND",+ "type": "power_in",+ "description": "Ground reference pin; the datasheet states the package TAB is electrically connected to GND on the DPAK package."+ },+ {+ "number": "3",+ "name": "OUTPUT",+ "type": "power_out",+ "description": "Regulated output voltage pin, labeled OUTPUT (top lead) in Figure 2 pin connections."+ }+ ],+ "provenance": {+ "extractor": "extract_pins 0.2",+ "factory_chain": {+ "factory": "2.0.0",+ "extractor": "extract_pins 0.2",+ "primary_model": "claude-sonnet-5",+ "primary_mode": "text+vision",+ "consensus_model": "claude-opus-4-8",+ "consensus": "agreed",+ "guards": "pin_guards 0.1: passed",+ "guard_notes": [+ "extractor flagged: The Figure 2 'Pin connections (top view)' drawing on page 4 identifies the DPAK (package outline SC0; This is a 3-terminal (fixed, non-inhibit) device: LF50ABDT-TRY is the DPAK order code without the 5-",+ "vision extraction: provenance cannot be text-verified; needs consensus"+ ],+ "pages_sent": 53,+ "cost_usd": 0.9744,+ "at": "2026-09-23T12:32:26"+ },+ "datasheet": {+ "url": "https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588943619692900352",+ "pages": 53,+ "sha256": "1867ecd27e7bf609",+ "source_tier": "lcsc"+ },+ "cad": "KiCad official (CC-BY-SA 4.0)",+ "pins": {+ "total": 3,+ "described": 3,+ "cites_pages": true,+ "refuses_to_fabricate": true+ }+ },+ "viewers": {+ "symbol": "viewers/symbol.html",+ "footprint": "viewers/footprint.html"+ }+ },+ "visibility": "public",+ "org": "adom",+ "author": {+ "name": "Ray",+ "email": "[email protected]"+ }+}