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Contents

README

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LF444ACN

Texas Instruments · Pre-ordered Chips · PDIP-14

LF444ACN from Texas Instruments, in a PDIP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OUT1 output Output of amplifier 1.
2 IN1- input Inverting input of amplifier 1; JFET input, differential input voltage up to ±30V (±38V for LF444A).
3 IN1+ input Non-inverting input of amplifier 1; JFET input with 10^12 Ω input resistance.
4 V+ power_in Positive supply voltage; absolute maximum ±22V for LF444A (±18V for LF444) across the supplies.
5 IN2+ input Non-inverting input of amplifier 2.
6 IN2- input Inverting input of amplifier 2.
7 OUT2 output Output of amplifier 2.
8 OUT3 output Output of amplifier 3.
9 IN3- input Inverting input of amplifier 3.
10 IN3+ input Non-inverting input of amplifier 3.
11 V- power_in Negative supply voltage; input voltages must not exceed the negative supply, and common-mode offset may increase within 3V of it.
12 IN4+ input Non-inverting input of amplifier 4.
13 IN4- input Inverting input of amplifier 4.
14 OUT4 output Output of amplifier 4.

Key specifications

Parameter Value
Manufacturer Texas Instruments
Package PDIP-14
Category Interface ICs
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage -22 22 V LF444A 2
Differential Input Voltage -38 38 V LF444A 2
Input Voltage Range -19 19 V LF444A 2
Power Dissipation 900 mW NAK Package 2
Maximum Junction Temperature Tj max 150 °C NAK Package 2
Storage Temperature Range -65 150 °C TA 2
Soldering Temperature, Dual-In-Line 260 °C Soldering, 10 sec. 2
Thermal Resistance Junction-Ambient θjA 100 °C/W Typical, NAK Package 2
Operating Temperature Range (commercial) TA 0 70 °C LF444A commercial range 2
Input Offset Voltage VOS 2 5 mV RS = 10k, TA = 25°C 2
Input Offset Voltage VOS 6.5 mV RS = 10k, 0°C ≤ TA ≤ +70°C 2
Input Offset Current IOS 5 25 pA VS = ±15V, Tj = 25°C 2
Input Offset Current IOS 1.5 nA VS = ±15V, Tj = 70°C 2
Input Bias Current IB 10 50 pA VS = ±15V, Tj = 25°C 2
Input Bias Current IB 3 nA VS = ±15V, Tj = 70°C 2
Large Signal Voltage Gain AVOL 50 100 V/mV VS = ±15V, VO = ±10V, RL = 10 kΩ, TA = 25°C 3
Large Signal Voltage Gain AVOL 25 V/mV Over Temperature 3
Output Voltage Swing VO -12 13 12 V VS = ±15V, RL = 10 kΩ 3
Input Common-Mode Voltage Range VCM 16 18 V positive range 3
Input Common-Mode Voltage Range VCM -17 V negative range 3
Common-Mode Rejection Ratio CMRR 80 100 dB RS ≤ 10 kΩ 3
Supply Voltage Rejection Ratio PSRR 80 100 dB See(3) 3
Supply Current IS 0.6 0.8 mA 3
Average TC of Input Offset Voltage ΔVOS/ΔT 10 μV/°C RS = 10 kΩ 2
Amplifier-to-Amplifier Coupling -120 dB 3
Slew Rate SR 1 V/μs VS = ±15V, TA = 25°C 3
Gain-Bandwidth Product GBW 1 MHz VS = ±15V, TA = 25°C 3
Equivalent Input Noise Voltage en 35 nV/√Hz TA = 25°C, RS = 100Ω, f = 1 kHz 3
Equivalent Input Noise Current in 0.01 pA/√Hz TA = 25°C, f = 1 kHz 3

CAD (KiCad official)

  • Symbol: LF444ACN
  • Footprint: Package_DIP:DIP-14_W7.62mm
  • 3D model: PDIP-14 (KiCad packages3D, STEP)
  • 3D model files: lf444acn-etched.step / lf444acn-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); lf444acn.step / lf444acn.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Texas Instruments datasheet (20 pp, sha256 0257d5a9c8584304, retrieved 2026-10-23, tier: manufacturer)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF