# LESD3Z5.0T1G

**LRC** · ESD And Surge Protection (TVS/ESD) · SOD-323

LESD3Z5.0T1G from LRC, in a SOD-323. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | K | passive | Cathode: the banded/marked end per the datasheet; pad 1 of the KiCad diode footprint. |
| 2 | A | passive | Anode. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | LRC |
| Package | SOD-323 |
| Category | Circuit Protection |
| Pins | 2 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Working Peak Reverse Voltage | VRWM |  |  | 5 | V |  | 2 |
| Maximum Reverse Leakage Current | IR |  |  | 10 | uA | @ VRWM=5V | 2 |
| Breakdown Voltage | VBR | 6 |  |  | V | @ It=1mA | 2 |
| Clamping Voltage | VC |  | 9.8 |  | V | @ IPP=5A, tp=8/20μs | 2 |
| Clamping Voltage | VC |  |  | 10.5 | V | @ IPP=24A, tp=8/20μs | 2 |
| Maximum Reverse Peak Pulse Current | IPP |  |  | 24 | A | tp=8/20μs | 2 |
| Capacitance | C |  | 350 |  | pF |  | 2 |
| Forward Voltage | VF |  | 0.9 |  | V | IF=10mA | 2 |
| Peak Pulse Power | PPK |  |  | 250 | W | tp = 8/20μs, Tamb=25°C | 1 |
| ESD Voltage | VESD |  |  | 30 | kV | HBM Waveform per IEC 61000-4-2 | 1 |
| Maximum lead temperature for soldering | TL |  |  | 260 | °C | during 10s | 1 |
| Storage Temperature Range | TSTG | -55 |  | 150 | °C |  | 1 |
| Maximum junction temperature | TJ | -55 |  | 125 | °C |  | 1 |

## CAD (KiCad official)

- Symbol: `LESD3Z5.0T1G`
- Footprint: `Diode_SMD:D_SOD-323`
- 3D model: SOD-323 (KiCad packages3D, STEP)
- 3D model files: `lesd3z5-0t1g-etched.step` / `lesd3z5-0t1g-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `lesd3z5-0t1g.step` / `lesd3z5-0t1g.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [LRC datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588903946693300224) (5 pp, sha256 `ed5e9e599da2580e`, retrieved 2026-10-22, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins`, primary `cathode-band convention` (convention), consensus `off` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/lesd3z5-0t1g-datasheet.pdf)