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LDTD114ELT1G

Public Made by Adom

by adom

LRC Digital Transistors, SOT-23. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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LDTD114ELT1G

LRC · Digital Transistors · SOT-23

LDTD114ELT1G from LRC, in a SOT-23. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 BASE input Base of the built-in bias-resistor NPN transistor, with R1 = 10 kΩ and R2 = 10 kΩ (device marking CA) integrated so the input needs no external resistor; input voltage is limited to −10 to +40 V.
2 EMITTER passive Emitter of the NPN transistor; the absolute maximum supply voltage VCC is 50 V and the maximum output current IC is 500 mA.
3 COLLECTOR passive Collector of the NPN transistor (output of the inverter stage); total power dissipation PD is limited to 200 mW and junction temperature Tj to 150 °C.

Key specifications

Parameter Value
Manufacturer LRC
Package SOT-23
Category Transistors/Thyristors
Pins 3

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage (off) VI(off) 0.5 V VCC=5V, IO=100µA 1
Input voltage (on) VI(on) 3 V VO=0.3V, IO=10mA 1
Output voltage (on) VO(on) 0.1 0.3 V IO/II=50mA/2.5mA 1
Input current II 0.88 mA VI=5V 1
Output current IO(off) 0.5 µA VCC=50V, VI=0V 1
Input resistance R1 7 10 13 kΩ 1
DC current gain GI 56 VO=5V, IO=50mA 1
Resistance ratio R2/R1 0.8 1 1.2 1
Supply voltage VCC 50 V Ta=25°C 1
Input voltage VIN -10 40 V Ta=25°C 1
Output current IC 500 mA Ta=25°C 1
Power dissipation PD 200 mW Ta=25°C 1
Junction temperature Tj 150 °C Ta=25°C 1
Storage temperature Tstg -55 150 °C Ta=25°C 1

CAD (KiCad official)

  • Symbol: LDTD114ELT1G
  • Footprint: Package_TO_SOT_SMD:SOT-23
  • 3D model: SOT-23 (KiCad packages3D, STEP)
  • 3D model files: ldtd114elt1g-etched.step / ldtd114elt1g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ldtd114elt1g.step / ldtd114elt1g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: LRC datasheet (3 pp, sha256 e375a40c404c165d, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF